bjorn3 added the cranelift label to Issue #7865.
bjorn3 added the bug label to Issue #7865.
bjorn3 opened issue #7865:
.clif
Test Casetest compile set opt_level=speed target x86_64 function u0:9(i8) -> i16 system_v { block0(v0: i8): v8 = sextend.i16 v0 v9 = imul v8, v8 v10 = iconst.i64 1000 v13 = sshr v9, v10 ; v10 = 1000 return v13 }
Steps to Reproduce
- Compile the above test case.
Expected Results
Compiles fine and masks the shift amount as expected.
Actual Results
Panics with "should be implemented in ISLE: inst = v12 = smulhi.i8 v0, v0, type = Some(types::I8)"
Versions and Environment
Cranelift version or commit: Tested with 0.104 and b6a8abc6ce31cf6db7ad5edb9b2567620190ce35.
Operating system: N/A
Architecture: x86_64
Extra Info
Reported to cg_clif by @cbeuw in https://github.com/rust-lang/rustc_codegen_cranelift/issues/1455.
alexcrichton closed issue #7865:
.clif
Test Casetest compile set opt_level=speed target x86_64 function u0:9(i8) -> i16 system_v { block0(v0: i8): v8 = sextend.i16 v0 v9 = imul v8, v8 v10 = iconst.i64 1000 v13 = sshr v9, v10 ; v10 = 1000 return v13 }
Steps to Reproduce
- Compile the above test case.
Expected Results
Compiles fine and masks the shift amount as expected.
Actual Results
Panics with "should be implemented in ISLE: inst = v12 = smulhi.i8 v0, v0, type = Some(types::I8)"
Versions and Environment
Cranelift version or commit: Tested with 0.104 and b6a8abc6ce31cf6db7ad5edb9b2567620190ce35.
Operating system: N/A
Architecture: x86_64
Extra Info
Reported to cg_clif by @cbeuw in https://github.com/rust-lang/rustc_codegen_cranelift/issues/1455.
Last updated: Dec 23 2024 at 13:07 UTC