Wasmtime GitHub notifications bot (Oct 08 2023 at 13:49): Wasmtime GitHub notifications bot (Oct 08 2023 at 13:49):afonso360 opened issue #7190:
:wave: Hey,
In the RISC-V backend the clobber save and restore implementations use a negative SP offset. We should switch these to always use a positive SP offset.
When the Compressed instruction extension is enabled we have access to
c.l*spandc.s*spwhich allow us to store and load any register into the stack using a positive SP offset.Implementing this as a positive offset has no downsides even when the C extension is disabled. So there isn't very much of a downside to this.
Wasmtime GitHub notifications bot (Oct 08 2023 at 13:49):afonso360 added the cranelift:area:riscv64 label to Issue #7190.
Wasmtime GitHub notifications bot (Oct 08 2023 at 13:49):afonso360 edited issue #7190:
:wave: Hey,
In the RISC-V backend the clobber save and restore implementations use a negative SP offset. We should switch these to always use a positive SP offset.
When the Compressed instruction extension is enabled we have access to
c.l*spandc.s*spwhich allow us to store and load any register into the stack using a positive SP offset.Implementing this as a positive offset has no downsides when the C extension is disabled. So there isn't very much of a downside to this.
Wasmtime GitHub notifications bot (Oct 08 2023 at 13:50):afonso360 edited issue #7190:
:wave: Hey,
In the RISC-V backend the clobber save and restore implementations use a negative SP offset. We should switch these to always use a positive SP offset.
When the Compressed instruction extension is enabled we have access to
c.l*spandc.s*spwhich allow us to store and load any register into the stack using a positive SP offset.Using these instruction in the prologue and epilogue would be nice due to lower instruction footprints.
Implementing this as a positive offset has no downsides when the C extension is disabled. So there isn't very much of a downside to this.
Wasmtime GitHub notifications bot (Oct 08 2023 at 13:52):afonso360 edited issue #7190:
:wave: Hey,
In the RISC-V backend the clobber save and restore implementations use a negative SP offset. We should switch these to always use a positive SP offset.
When the Compressed instruction extension is enabled we have access to
c.ldspandc.sdspwhich allow us to store and load any register into the stack using a positive SP offset.Using these instruction in the prologue and epilogue would be nice due to lower instruction footprints.
Implementing this as a positive offset has no downsides when the C extension is disabled. So there isn't very much of a downside to this.
Wasmtime GitHub notifications bot (Oct 08 2023 at 20:06):afonso360 edited issue #7190:
:wave: Hey,
In the RISC-V backend the clobber save and restore implementation uses a negative SP offset. We should switch it to always use a positive SP offset.
When the Compressed instruction extension is enabled we have access to
c.ldspandc.sdspwhich allow us to store and load any register into the stack using a positive SP offset.Using these instruction in the prologue and epilogue would be nice due to lower instruction footprints.
Implementing this as a positive offset has no downsides when the C extension is disabled. So there isn't very much of a downside to this.
Wasmtime GitHub notifications bot (Oct 08 2023 at 20:06):afonso360 edited issue #7190:
:wave: Hey,
In the RISC-V backend the clobber save and restore implementation uses a negative SP offset. We should switch it to always use a positive SP offset.
When the Compressed instruction extension is enabled we have access to
c.ldspandc.sdspwhich allow us to store and load any register into the stack using a positive SP offset.Using these instruction in the prologue and epilogue would be nice due to the lower instruction footprint.
Implementing this as a positive offset has no downsides when the C extension is disabled. So there isn't very much of a downside to this.
Last updated: Nov 22 2024 at 16:03 UTC