wasmtime / issue #6786 riscv64: Missing implementations f... · git-wasmtime

Stream: git-wasmtime

Topic: wasmtime / issue #6786 riscv64: Missing implementations f...

Wasmtime GitHub notifications bot (Jul 31 2023 at 04:22):

candymate opened issue #6786:

Test Case

Any cases with v128.loadXXX or v128.storeXXX would work

One example

(module
  (type (;0;) (func (param i32 v128)))
  (func (;0;) (type 0) (param i32 v128)
    local.get 0
    local.get 1
    v128.store16_lane align=1 0
  )
  (export "main" (func 0))
)

Steps to Reproduce

Compiling any cases containing v128.loadXXX or v128.storeXXX leads to reaching unreachable code.
Such compilations lead to reaching the following codes

// cranelift/codegen/src/isa/riscv64/inst/args.rs:1289
pub(crate) fn from_type(t: Type) -> Self {
    if t.is_float() {
        return if t == F32 { Self::Flw } else { Self::Fld };
    }
    match t {
        R32 => Self::Lwu,
        R64 | I64 => Self::Ld,

        I8 => Self::Lb,
        I16 => Self::Lh,
        I32 => Self::Lw,
        _ => unreachable!(), // reaches here
    }
}

// cranelift/codegen/src/isa/riscv64/inst/args.rs:1338
pub(crate) fn from_type(t: Type) -> Self {
    if t.is_float() {
        return if t == F32 { Self::Fsw } else { Self::Fsd };
    }
    match t.bits() {
        1 | 8 => Self::Sb,
        16 => Self::Sh,
        32 => Self::Sw,
        64 => Self::Sd,
        _ => unreachable!(), // reaches here
    }
}

Steps are the following:

git submodule update --init
cargo run --release --target=riscv64gc-unknown-linux-gnu test.wasm

Expected Results

Successful compilation

Actual Results

Panics with 'internal error: entered unreachable code'

Versions and Environment

Wasmtime version or commit: v11.0.1 Release

Operating system: Ubuntu 20.04.6

Architecture: RISC-V64

Wasmtime GitHub notifications bot (Jul 31 2023 at 04:22):

candymate added the bug label to Issue #6786.

Wasmtime GitHub notifications bot (Jul 31 2023 at 04:44):

cfallin commented on issue #6786:

SIMD support on RISC-V is still a work-in-progress; @afonso360 was contributing code a few opcodes at a time recently. So it's expected that this doesn't yet work, though contributions are welcome if you're interested in tackling this!

Wasmtime GitHub notifications bot (Jul 31 2023 at 08:43):

afonso360 commented on issue #6786:

:wave: Hey,

This code should work, but SIMD support only works on machines with Vector extensions.

Are you running this natively on a RISC-V machine? Or just using QEMU?

If you are running on QEMU you can add the following parameter to make -cpu rv64,v=true,vlen=128,vext_spec=v1.0 this compile and run.

If you are running on an actual RISC-V machine, please make sure it supports version 1.0 of the Vector Extension. I haven't tested with 0.7.1 (popular in a lot of current CPU's) but I doubt it would work since they are somewhat incompatible.

That being said, we should probably have a better error message for this stuff.

Wasmtime GitHub notifications bot (Jul 31 2023 at 08:44):

afonso360 edited a comment on issue #6786:

:wave: Hey,

This code should work, but SIMD support only works on machines with Vector extensions.

Are you running this natively on a RISC-V machine? Or just using QEMU?

If you are running on QEMU you can add the following parameter -cpu rv64,v=true,vlen=128,vext_spec=v1.0 to make this compile and run.

If you are running on an actual RISC-V machine, please make sure it supports version 1.0 of the Vector Extension. I haven't tested with 0.7.1 (popular in a lot of current CPU's) but I doubt it would work since they are somewhat incompatible.

That being said, we should probably have a better error message for this stuff.

Wasmtime GitHub notifications bot (Jul 31 2023 at 08:51):

afonso360 added the cranelift:area:riscv64 label to Issue #6786.

Wasmtime GitHub notifications bot (Jul 31 2023 at 08:52):

afonso360 edited a comment on issue #6786:

:wave: Hey,

This code should work, but SIMD support only works on machines with Vector extensions.

Are you running this natively on a RISC-V machine, or just using QEMU?

If you are running on QEMU you can add the following parameter -cpu rv64,v=true,vlen=128,vext_spec=v1.0 to make this compile and run.

If you are running on an actual RISC-V machine, please make sure it supports version 1.0 of the Vector Extension. I haven't tested with 0.7.1 (popular in a lot of current CPU's) but I doubt it would work since they are somewhat incompatible.

That being said, we should probably have a better error message for this stuff.

Wasmtime GitHub notifications bot (Jul 31 2023 at 08:52):

afonso360 edited a comment on issue #6786:

:wave: Hey,

This code should work, but SIMD support only works on machines with Vector extensions.

Are you running this natively on a RISC-V machine, or just using QEMU?

If you are running on QEMU you can add the following parameter -cpu rv64,v=true,vlen=128,vext_spec=v1.0 to the QEMU arguments to make this compile and run.

If you are running on an actual RISC-V machine, please make sure it supports version 1.0 of the Vector Extension. I haven't tested with 0.7.1 (popular in a lot of current CPU's) but I doubt it would work since they are somewhat incompatible.

That being said, we should probably have a better error message for this stuff.

Wasmtime GitHub notifications bot (Jul 31 2023 at 09:06):

afonso360 edited a comment on issue #6786:

:wave: Hey,

This code should work, but SIMD support only works on machines with Vector extensions.

Are you running this natively on a RISC-V machine, or just using QEMU?

If you are running on QEMU you can add the following parameter -cpu rv64,v=true,vlen=128,vext_spec=v1.0 to the QEMU arguments to make this compile and run.

If you are running on an actual RISC-V machine, please make sure it supports version 1.0 of the Vector Extension and that this is reported in /proc/cpuinfo. I haven't tested with 0.7.1 (popular in a lot of current CPU's) but I doubt it would work since they are somewhat incompatible.

That being said, we should probably have a better error message for this stuff.

Wasmtime GitHub notifications bot (Aug 01 2023 at 02:34):

candymate commented on issue #6786:

Hi,

I'm currently running QEMU, so I added the parameter you gave me. But, it doesn't change anything.

In ~/.cargo/config.toml, I have the following:
[target.riscv64gc-unknown-linux-gnu]
linker = "riscv64-linux-gnu-gcc"
runner = "qemu-riscv64 -cpu rv64,v=true,vlen=128,vext_spec=v1.0 -L /usr/riscv64-linux-gnu -E LD_LIBRARY_PATH=/usr/riscv64-linux-gnu/lib -E WASMTIME_TEST_NO_HOG_MEMORY=1"
Just in case, I upgraded Ubuntu to 22.04, and built qemu-riscv64 from the latest version of riscv-gnu-toolchain. (https://github.com/riscv-collab/riscv-gnu-toolchain)

Versions I'm using are the following:
$ qemu-riscv64 --version
qemu-riscv64 version 7.1.0 (v7.1.0)
$ riscv64-linux-gnu-gcc --version
riscv64-linux-gnu-gcc (Ubuntu 11.4.0-1ubuntu1~22.04) 11.4.0
Still leads to the following error message. (Ran with a simple wrapper to provide Wasm memory)
     Running `qemu-riscv64 -cpu rv64,v=true,vlen=128,vext_spec=v1.0 -L /usr/riscv64-linux-gnu -E LD_LIBRARY_PATH=/usr/riscv64-linux-gnu/lib -E WASMTIME_TEST_NO_HOG_MEMORY=1 target/riscv64gc-unknown-linux-gnu/debug/wasmtime-wrapper input`
thread '<unnamed>' panicked at 'internal error: entered unreachable code', /home/candymate/.cargo/registry/src/index.crates.io-6f17d22bba15001f/cranelift-codegen-0.98.1/src/isa/riscv64/inst/args.rs:1347:18
note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace
It would be helpful if you tell me what I'm missing.

Wasmtime GitHub notifications bot (Aug 01 2023 at 02:37):

candymate edited a comment on issue #6786:

Hi,

I'm currently running QEMU, so I added the parameter you gave me. But, it doesn't change anything.

In ~/.cargo/config.toml, I have the following:
[target.riscv64gc-unknown-linux-gnu]
linker = "riscv64-linux-gnu-gcc"
runner = "qemu-riscv64 -cpu rv64,v=true,vlen=128,vext_spec=v1.0 -L /usr/riscv64-linux-gnu -E LD_LIBRARY_PATH=/usr/riscv64-linux-gnu/lib -E WASMTIME_TEST_NO_HOG_MEMORY=1"
Just in case, I upgraded Ubuntu to 22.04, and built qemu-riscv64 from the latest version of riscv-gnu-toolchain. (https://github.com/riscv-collab/riscv-gnu-toolchain)

Versions I'm using are the following:
$ rustc --version
rustc 1.71.0-nightly (ce5919fce 2023-05-15)
$ qemu-riscv64 --version
qemu-riscv64 version 7.1.0 (v7.1.0)
$ riscv64-linux-gnu-gcc --version
riscv64-linux-gnu-gcc (Ubuntu 11.4.0-1ubuntu1~22.04) 11.4.0
Still leads to the following error message. (Ran with a simple wrapper to provide Wasm memory)
     Running `qemu-riscv64 -cpu rv64,v=true,vlen=128,vext_spec=v1.0 -L /usr/riscv64-linux-gnu -E LD_LIBRARY_PATH=/usr/riscv64-linux-gnu/lib -E WASMTIME_TEST_NO_HOG_MEMORY=1 target/riscv64gc-unknown-linux-gnu/debug/wasmtime-wrapper input`
thread '<unnamed>' panicked at 'internal error: entered unreachable code', /home/candymate/.cargo/registry/src/index.crates.io-6f17d22bba15001f/cranelift-codegen-0.98.1/src/isa/riscv64/inst/args.rs:1347:18
note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace
It would be helpful if you tell me what I'm missing.

Wasmtime GitHub notifications bot (Aug 01 2023 at 02:37):

candymate edited a comment on issue #6786:

Hi,

I'm currently running QEMU, so I added the parameter you gave me. But, it doesn't change anything.

In ~/.cargo/config.toml, I have the following:

[target.riscv64gc-unknown-linux-gnu]
linker = "riscv64-linux-gnu-gcc"
runner = "qemu-riscv64 -cpu rv64,v=true,vlen=128,vext_spec=v1.0 -L /usr/riscv64-linux-gnu -E LD_LIBRARY_PATH=/usr/riscv64-linux-gnu/lib -E WASMTIME_TEST_NO_HOG_MEMORY=1"

Just in case, I upgraded Ubuntu to 22.04, and built qemu-riscv64 from the latest version of riscv-gnu-toolchain. (https://github.com/riscv-collab/riscv-gnu-toolchain)

Versions I'm using are the following:

$ cargo --version
cargo 1.71.0-nightly (13413c64f 2023-05-10)
$ rustc --version
rustc 1.71.0-nightly (ce5919fce 2023-05-15)
$ qemu-riscv64 --version
qemu-riscv64 version 7.1.0 (v7.1.0)
$ riscv64-linux-gnu-gcc --version
riscv64-linux-gnu-gcc (Ubuntu 11.4.0-1ubuntu1~22.04) 11.4.0

Still leads to the following error message. (Ran with a simple wrapper to provide Wasm memory)

     Running `qemu-riscv64 -cpu rv64,v=true,vlen=128,vext_spec=v1.0 -L /usr/riscv64-linux-gnu -E LD_LIBRARY_PATH=/usr/riscv64-linux-gnu/lib -E WASMTIME_TEST_NO_HOG_MEMORY=1 target/riscv64gc-unknown-linux-gnu/debug/wasmtime-wrapper input`
thread '<unnamed>' panicked at 'internal error: entered unreachable code', /home/candymate/.cargo/registry/src/index.crates.io-6f17d22bba15001f/cranelift-codegen-0.98.1/src/isa/riscv64/inst/args.rs:1347:18
note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace

It would be helpful if you tell me what I'm missing.

Wasmtime GitHub notifications bot (Aug 01 2023 at 11:09):

afonso360 commented on issue #6786:

Oh! Right, QEMU only gained the ability to emulate /proc/cpuinfo in version 8.1, we use that to detect the features of the processor and automatically enable them.

To manually force it on, you can use the wasmtime flag --cranelift-enable has_v, which should forcefully enable them on our side.

Wasmtime GitHub notifications bot (Aug 02 2023 at 02:27):

candymate commented on issue #6786:

Adding the has_v flag solved the problem. Thanks!

Wasmtime GitHub notifications bot (Aug 02 2023 at 02:27):

candymate closed issue #6786:

Test Case

Any cases with v128.loadXXX or v128.storeXXX would work

One example

(module
  (type (;0;) (func (param i32 v128)))
  (func (;0;) (type 0) (param i32 v128)
    local.get 0
    local.get 1
    v128.store16_lane align=1 0
  )
  (export "main" (func 0))
)

Steps to Reproduce

Compiling any cases containing v128.loadXXX or v128.storeXXX leads to reaching unreachable code.
Such compilations lead to reaching the following codes

// cranelift/codegen/src/isa/riscv64/inst/args.rs:1289
pub(crate) fn from_type(t: Type) -> Self {
    if t.is_float() {
        return if t == F32 { Self::Flw } else { Self::Fld };
    }
    match t {
        R32 => Self::Lwu,
        R64 | I64 => Self::Ld,

        I8 => Self::Lb,
        I16 => Self::Lh,
        I32 => Self::Lw,
        _ => unreachable!(), // reaches here
    }
}

// cranelift/codegen/src/isa/riscv64/inst/args.rs:1338
pub(crate) fn from_type(t: Type) -> Self {
    if t.is_float() {
        return if t == F32 { Self::Fsw } else { Self::Fsd };
    }
    match t.bits() {
        1 | 8 => Self::Sb,
        16 => Self::Sh,
        32 => Self::Sw,
        64 => Self::Sd,
        _ => unreachable!(), // reaches here
    }
}

Steps are the following:

git submodule update --init
cargo run --release --target=riscv64gc-unknown-linux-gnu test.wasm

Expected Results

Successful compilation

Actual Results

Panics with 'internal error: entered unreachable code'

Versions and Environment

Wasmtime version or commit: v11.0.1 Release

Operating system: Ubuntu 20.04.6

Architecture: RISC-V64

Last updated: Dec 23 2024 at 12:05 UTC