yuyang-ok commented on issue #5845:
LGTM! I'm not 100% sure about the regalloc changes, if someone else could double check that, it would be nice.
I think regalloc changes work same In current situation, I thinktmp
register used multi time usually, betterreg_early_def
.
yuyang-ok edited a comment on issue #5845:
LGTM! I'm not 100% sure about the regalloc changes, if someone else could double check that, it would be nice.
I think regalloc changes work same In current situation, I think
tmp
register used multi time usually, betterreg_early_def
.
yuyang-ok edited a comment on issue #5845:
LGTM! I'm not 100% sure about the regalloc changes, if someone else could double check that, it would be nice.
I think regalloc changes works same In current situation, I think
tmp
register used multi time usually, betterreg_early_def
.
yuyang-ok edited a comment on issue #5845:
LGTM! I'm not 100% sure about the regalloc changes, if someone else could double check that, it would be nice.
I think regalloc changes works same in current situation, I think
tmp
register used multi time usually, betterreg_early_def
.
yuyang-ok edited a comment on issue #5845:
LGTM! I'm not 100% sure about the regalloc changes, if someone else could double check that, it would be nice.
I think regalloc changes works same in current situation, I think
rd
register used multi time usually, betterreg_early_def
.
yuyang-ok edited a comment on issue #5845:
LGTM! I'm not 100% sure about the regalloc changes, if someone else could double check that, it would be nice.
I think regalloc changes works same in current situation, I think
rd
register used multi time, betterreg_early_def
.
alexcrichton commented on issue #5845:
I think the failure in this test run was legitimate, namely the new
*.clif
test added in this PR is panicking on the x64 backend. I think it's ok to remove thetarget x86_64
line and file an issue to let this PR land.
jameysharp commented on issue #5845:
I can confirm that the new CLIF test fails on x86_64 while emitting machine code for the
CvtFloatToSintSeq
pseudoinstruction. I think none of the float-to-int variants (saturating or trapping, signed or unsigned) are implemented in the x64 backend for types other than I32 and I64, but I'm not absolutely sure I read the ISLE rules correctly.
yuyang-ok commented on issue #5845:
@alexcrichton I have remove test for
x86_64
.
jameysharp commented on issue #5845:
@yuyang-ok, thank you!
Last updated: Dec 23 2024 at 12:05 UTC