afonso360 labeled issue #5839:
:wave: Hey,
.clif
Test Casetest interpret test run set opt_level=speed target riscv64gc function %a(i8, i8) -> i32 { block0(v0: i8, v1: i8): v2 = icmp sle v0, v1 v3 = uextend.i32 v2 v4 = iconst.i32 0 v5 = iconst.i32 1 v6 = icmp.i32 eq v3, v4 ; v4 = 0 v7 = select v6, v5, v3 ; v5 = 1 return v7 } ; run: %a(20, -11) == 1
Steps to Reproduce
clif-util test ./the-above.clif
Expected Results
The test to pass
Actual Results
Running `qemu-riscv64 -L /usr/riscv64-linux-gnu -E LD_LIBRARY_PATH=/usr/riscv64-linux-gnu/lib /home/afonso/git/wasmtime/target/riscv64gc-unknown-linux-gnu/debug/clif-util test ./lmao.clif` ERROR cranelift_filetests::concurrent > FAIL: run FAIL ./lmao.clif: run Caused by: Failed test: run: %a(20, -11) == 1, actual: 0 1 tests Error: 1 failure
Versions and Environment
Cranelift version or commit: 1e6c94bec1a56a88ea3df518de0d073d26596580 (current main)
Operating system: Linux
Architecture: RISC-V
Extra Info
This testcase only fails with
opt_level=speed
, without it, it passes.<details>
<summary>Disassembly withopt_level=none
</summary>Disassembly of 72 bytes: 0: 13 18 85 03 slli a6, a0, 0x38 4: 13 58 88 43 srai a6, a6, 0x38 8: 13 9e 85 03 slli t3, a1, 0x38 c: 13 5e 8e 43 srai t3, t3, 0x38 10: 63 46 0e 01 blt t3, a6, 0xc 14: 93 02 10 00 addi t0, zero, 1 18: 6f 00 80 00 j 8 1c: 93 02 00 00 mv t0, zero 20: 13 fe f2 0f andi t3, t0, 0xff 24: 1b 07 0e 00 sext.w a4, t3 28: 13 08 00 00 mv a6, zero 2c: 9b 0e 08 00 sext.w t4, a6 30: 93 02 10 00 addi t0, zero, 1 34: 63 06 d7 01 beq a4, t4, 0xc 38: 13 65 0e 00 ori a0, t3, 0 3c: 6f 00 80 00 j 8 40: 13 e5 02 00 ori a0, t0, 0 44: 67 80 00 00 ret
</details>
<details>
<summary>Disassembly withopt_level=speed
</summary>Disassembly of 68 bytes: 0: 93 08 10 00 addi a7, zero, 1 4: 93 17 85 03 slli a5, a0, 0x38 8: 93 d7 87 43 srai a5, a5, 0x38 c: 13 9e 85 03 slli t3, a1, 0x38 10: 13 5e 8e 43 srai t3, t3, 0x38 14: 63 46 fe 00 blt t3, a5, 0xc 18: 93 0e 10 00 addi t4, zero, 1 1c: 6f 00 80 00 j 8 20: 93 0e 00 00 mv t4, zero 24: 13 fe fe 0f andi t3, t4, 0xff 28: 93 77 f5 0f andi a5, a0, 0xff 2c: 93 fe f5 0f andi t4, a1, 0xff 30: 63 c6 fe 00 blt t4, a5, 0xc 34: 13 65 0e 00 ori a0, t3, 0 38: 6f 00 80 00 j 8 3c: 13 e5 08 00 ori a0, a7, 0 40: 67 80 00 00 ret
</details>
cc: @yuyang-ok
afonso360 opened issue #5839:
:wave: Hey,
.clif
Test Casetest interpret test run set opt_level=speed target riscv64gc function %a(i8, i8) -> i32 { block0(v0: i8, v1: i8): v2 = icmp sle v0, v1 v3 = uextend.i32 v2 v4 = iconst.i32 0 v5 = iconst.i32 1 v6 = icmp.i32 eq v3, v4 ; v4 = 0 v7 = select v6, v5, v3 ; v5 = 1 return v7 } ; run: %a(20, -11) == 1
Steps to Reproduce
clif-util test ./the-above.clif
Expected Results
The test to pass
Actual Results
Running `qemu-riscv64 -L /usr/riscv64-linux-gnu -E LD_LIBRARY_PATH=/usr/riscv64-linux-gnu/lib /home/afonso/git/wasmtime/target/riscv64gc-unknown-linux-gnu/debug/clif-util test ./lmao.clif` ERROR cranelift_filetests::concurrent > FAIL: run FAIL ./lmao.clif: run Caused by: Failed test: run: %a(20, -11) == 1, actual: 0 1 tests Error: 1 failure
Versions and Environment
Cranelift version or commit: 1e6c94bec1a56a88ea3df518de0d073d26596580 (current main)
Operating system: Linux
Architecture: RISC-V
Extra Info
This testcase only fails with
opt_level=speed
, without it, it passes.<details>
<summary>Disassembly withopt_level=none
</summary>Disassembly of 72 bytes: 0: 13 18 85 03 slli a6, a0, 0x38 4: 13 58 88 43 srai a6, a6, 0x38 8: 13 9e 85 03 slli t3, a1, 0x38 c: 13 5e 8e 43 srai t3, t3, 0x38 10: 63 46 0e 01 blt t3, a6, 0xc 14: 93 02 10 00 addi t0, zero, 1 18: 6f 00 80 00 j 8 1c: 93 02 00 00 mv t0, zero 20: 13 fe f2 0f andi t3, t0, 0xff 24: 1b 07 0e 00 sext.w a4, t3 28: 13 08 00 00 mv a6, zero 2c: 9b 0e 08 00 sext.w t4, a6 30: 93 02 10 00 addi t0, zero, 1 34: 63 06 d7 01 beq a4, t4, 0xc 38: 13 65 0e 00 ori a0, t3, 0 3c: 6f 00 80 00 j 8 40: 13 e5 02 00 ori a0, t0, 0 44: 67 80 00 00 ret
</details>
<details>
<summary>Disassembly withopt_level=speed
</summary>Disassembly of 68 bytes: 0: 93 08 10 00 addi a7, zero, 1 4: 93 17 85 03 slli a5, a0, 0x38 8: 93 d7 87 43 srai a5, a5, 0x38 c: 13 9e 85 03 slli t3, a1, 0x38 10: 13 5e 8e 43 srai t3, t3, 0x38 14: 63 46 fe 00 blt t3, a5, 0xc 18: 93 0e 10 00 addi t4, zero, 1 1c: 6f 00 80 00 j 8 20: 93 0e 00 00 mv t4, zero 24: 13 fe fe 0f andi t3, t4, 0xff 28: 93 77 f5 0f andi a5, a0, 0xff 2c: 93 fe f5 0f andi t4, a1, 0xff 30: 63 c6 fe 00 blt t4, a5, 0xc 34: 13 65 0e 00 ori a0, t3, 0 38: 6f 00 80 00 j 8 3c: 13 e5 08 00 ori a0, a7, 0 40: 67 80 00 00 ret
</details>
cc: @yuyang-ok
afonso360 labeled issue #5839:
:wave: Hey,
.clif
Test Casetest interpret test run set opt_level=speed target riscv64gc function %a(i8, i8) -> i32 { block0(v0: i8, v1: i8): v2 = icmp sle v0, v1 v3 = uextend.i32 v2 v4 = iconst.i32 0 v5 = iconst.i32 1 v6 = icmp.i32 eq v3, v4 ; v4 = 0 v7 = select v6, v5, v3 ; v5 = 1 return v7 } ; run: %a(20, -11) == 1
Steps to Reproduce
clif-util test ./the-above.clif
Expected Results
The test to pass
Actual Results
Running `qemu-riscv64 -L /usr/riscv64-linux-gnu -E LD_LIBRARY_PATH=/usr/riscv64-linux-gnu/lib /home/afonso/git/wasmtime/target/riscv64gc-unknown-linux-gnu/debug/clif-util test ./lmao.clif` ERROR cranelift_filetests::concurrent > FAIL: run FAIL ./lmao.clif: run Caused by: Failed test: run: %a(20, -11) == 1, actual: 0 1 tests Error: 1 failure
Versions and Environment
Cranelift version or commit: 1e6c94bec1a56a88ea3df518de0d073d26596580 (current main)
Operating system: Linux
Architecture: RISC-V
Extra Info
This testcase only fails with
opt_level=speed
, without it, it passes.<details>
<summary>Disassembly withopt_level=none
</summary>Disassembly of 72 bytes: 0: 13 18 85 03 slli a6, a0, 0x38 4: 13 58 88 43 srai a6, a6, 0x38 8: 13 9e 85 03 slli t3, a1, 0x38 c: 13 5e 8e 43 srai t3, t3, 0x38 10: 63 46 0e 01 blt t3, a6, 0xc 14: 93 02 10 00 addi t0, zero, 1 18: 6f 00 80 00 j 8 1c: 93 02 00 00 mv t0, zero 20: 13 fe f2 0f andi t3, t0, 0xff 24: 1b 07 0e 00 sext.w a4, t3 28: 13 08 00 00 mv a6, zero 2c: 9b 0e 08 00 sext.w t4, a6 30: 93 02 10 00 addi t0, zero, 1 34: 63 06 d7 01 beq a4, t4, 0xc 38: 13 65 0e 00 ori a0, t3, 0 3c: 6f 00 80 00 j 8 40: 13 e5 02 00 ori a0, t0, 0 44: 67 80 00 00 ret
</details>
<details>
<summary>Disassembly withopt_level=speed
</summary>Disassembly of 68 bytes: 0: 93 08 10 00 addi a7, zero, 1 4: 93 17 85 03 slli a5, a0, 0x38 8: 93 d7 87 43 srai a5, a5, 0x38 c: 13 9e 85 03 slli t3, a1, 0x38 10: 13 5e 8e 43 srai t3, t3, 0x38 14: 63 46 fe 00 blt t3, a5, 0xc 18: 93 0e 10 00 addi t4, zero, 1 1c: 6f 00 80 00 j 8 20: 93 0e 00 00 mv t4, zero 24: 13 fe fe 0f andi t3, t4, 0xff 28: 93 77 f5 0f andi a5, a0, 0xff 2c: 93 fe f5 0f andi t4, a1, 0xff 30: 63 c6 fe 00 blt t4, a5, 0xc 34: 13 65 0e 00 ori a0, t3, 0 38: 6f 00 80 00 j 8 3c: 13 e5 08 00 ori a0, a7, 0 40: 67 80 00 00 ret
</details>
cc: @yuyang-ok
afonso360 labeled issue #5839:
:wave: Hey,
.clif
Test Casetest interpret test run set opt_level=speed target riscv64gc function %a(i8, i8) -> i32 { block0(v0: i8, v1: i8): v2 = icmp sle v0, v1 v3 = uextend.i32 v2 v4 = iconst.i32 0 v5 = iconst.i32 1 v6 = icmp.i32 eq v3, v4 ; v4 = 0 v7 = select v6, v5, v3 ; v5 = 1 return v7 } ; run: %a(20, -11) == 1
Steps to Reproduce
clif-util test ./the-above.clif
Expected Results
The test to pass
Actual Results
Running `qemu-riscv64 -L /usr/riscv64-linux-gnu -E LD_LIBRARY_PATH=/usr/riscv64-linux-gnu/lib /home/afonso/git/wasmtime/target/riscv64gc-unknown-linux-gnu/debug/clif-util test ./lmao.clif` ERROR cranelift_filetests::concurrent > FAIL: run FAIL ./lmao.clif: run Caused by: Failed test: run: %a(20, -11) == 1, actual: 0 1 tests Error: 1 failure
Versions and Environment
Cranelift version or commit: 1e6c94bec1a56a88ea3df518de0d073d26596580 (current main)
Operating system: Linux
Architecture: RISC-V
Extra Info
This testcase only fails with
opt_level=speed
, without it, it passes.<details>
<summary>Disassembly withopt_level=none
</summary>Disassembly of 72 bytes: 0: 13 18 85 03 slli a6, a0, 0x38 4: 13 58 88 43 srai a6, a6, 0x38 8: 13 9e 85 03 slli t3, a1, 0x38 c: 13 5e 8e 43 srai t3, t3, 0x38 10: 63 46 0e 01 blt t3, a6, 0xc 14: 93 02 10 00 addi t0, zero, 1 18: 6f 00 80 00 j 8 1c: 93 02 00 00 mv t0, zero 20: 13 fe f2 0f andi t3, t0, 0xff 24: 1b 07 0e 00 sext.w a4, t3 28: 13 08 00 00 mv a6, zero 2c: 9b 0e 08 00 sext.w t4, a6 30: 93 02 10 00 addi t0, zero, 1 34: 63 06 d7 01 beq a4, t4, 0xc 38: 13 65 0e 00 ori a0, t3, 0 3c: 6f 00 80 00 j 8 40: 13 e5 02 00 ori a0, t0, 0 44: 67 80 00 00 ret
</details>
<details>
<summary>Disassembly withopt_level=speed
</summary>Disassembly of 68 bytes: 0: 93 08 10 00 addi a7, zero, 1 4: 93 17 85 03 slli a5, a0, 0x38 8: 93 d7 87 43 srai a5, a5, 0x38 c: 13 9e 85 03 slli t3, a1, 0x38 10: 13 5e 8e 43 srai t3, t3, 0x38 14: 63 46 fe 00 blt t3, a5, 0xc 18: 93 0e 10 00 addi t4, zero, 1 1c: 6f 00 80 00 j 8 20: 93 0e 00 00 mv t4, zero 24: 13 fe fe 0f andi t3, t4, 0xff 28: 93 77 f5 0f andi a5, a0, 0xff 2c: 93 fe f5 0f andi t4, a1, 0xff 30: 63 c6 fe 00 blt t4, a5, 0xc 34: 13 65 0e 00 ori a0, t3, 0 38: 6f 00 80 00 j 8 3c: 13 e5 08 00 ori a0, a7, 0 40: 67 80 00 00 ret
</details>
cc: @yuyang-ok
yuyang-ok commented on issue #5839:
This is a little wired to me.
The code is change after alias analyze.
function u0:0(i8, i8) -> i32 system_v {
block0(v0: i8, v1: i8):
v2 = icmp sle v0, v1
v3 = uextend.i32 v2
v4 = iconst.i32 0
v5 = iconst.i32 1
v6 = icmp eq v3, v4 ; v4 = 0
v7 = select v6, v5, v3 ; v5 = 1
return v7
}
after alias analyze.
function u0:0(i8, i8) -> i32 system_v {
block0(v0: i8, v1: i8):
v8 = icmp sgt v0, v1
v5 = iconst.i32 1
v2 = icmp sle v0, v1
v3 = uextend.i32 v2
v7 = select v8, v5, v3 ; v5 = 1
return v7
}
yuyang-ok edited a comment on issue #5839:
This is a little wired to me.
The code is change after alias analyze.
function u0:0(i8, i8) -> i32 system_v {
block0(v0: i8, v1: i8):
v2 = icmp sle v0, v1
v3 = uextend.i32 v2
v4 = iconst.i32 0
v5 = iconst.i32 1
v6 = icmp eq v3, v4 ; v4 = 0
v7 = select v6, v5, v3 ; v5 = 1
return v7
}
after alias analyze.
function u0:0(i8, i8) -> i32 system_v {
block0(v0: i8, v1: i8):
v8 = icmp sgt v0, v1
v5 = iconst.i32 1
v2 = icmp sle v0, v1
v3 = uextend.i32 v2
v7 = select v8, v5, v3 ; v5 = 1
return v7
}
full log are.
[abc.log](https://github.com/bytecodealliance/wasmtime/files/10788973/abc.log)
yuyang-ok edited a comment on issue #5839:
This is a little wired to me.
The code has changed after alias analyze.
function u0:0(i8, i8) -> i32 system_v {
block0(v0: i8, v1: i8):
v2 = icmp sle v0, v1
v3 = uextend.i32 v2
v4 = iconst.i32 0
v5 = iconst.i32 1
v6 = icmp eq v3, v4 ; v4 = 0
v7 = select v6, v5, v3 ; v5 = 1
return v7
}
after alias analyze.
function u0:0(i8, i8) -> i32 system_v {
block0(v0: i8, v1: i8):
v8 = icmp sgt v0, v1
v5 = iconst.i32 1
v2 = icmp sle v0, v1
v3 = uextend.i32 v2
v7 = select v8, v5, v3 ; v5 = 1
return v7
}
full log are.
[abc.log](https://github.com/bytecodealliance/wasmtime/files/10788973/abc.log)
yuyang-ok edited a comment on issue #5839:
This is a little wired to me.
The code has changed after alias analyze.
function u0:0(i8, i8) -> i32 system_v {
block0(v0: i8, v1: i8):
v2 = icmp sle v0, v1
v3 = uextend.i32 v2
v4 = iconst.i32 0
v5 = iconst.i32 1
v6 = icmp eq v3, v4 ; v4 = 0
v7 = select v6, v5, v3 ; v5 = 1
return v7
}
after alias analyze.
function u0:0(i8, i8) -> i32 system_v {
block0(v0: i8, v1: i8):
v8 = icmp sgt v0, v1
v5 = iconst.i32 1
v2 = icmp sle v0, v1
v3 = uextend.i32 v2
v7 = select v8, v5, v3 ; v5 = 1
return v7
}
full log are.
[abc.log](https://github.com/bytecodealliance/wasmtime/files/10788973/abc.log)
v7 = select v8, v5, v3 ; v5 = 1
This is wired. How come a `icmp eq` can become a `icmp sgt`.
yuyang-ok deleted a comment on issue #5839:
This is a little wired to me.
The code has changed after alias analyze.
function u0:0(i8, i8) -> i32 system_v {
block0(v0: i8, v1: i8):
v2 = icmp sle v0, v1
v3 = uextend.i32 v2
v4 = iconst.i32 0
v5 = iconst.i32 1
v6 = icmp eq v3, v4 ; v4 = 0
v7 = select v6, v5, v3 ; v5 = 1
return v7
}
after alias analyze.
function u0:0(i8, i8) -> i32 system_v {
block0(v0: i8, v1: i8):
v8 = icmp sgt v0, v1
v5 = iconst.i32 1
v2 = icmp sle v0, v1
v3 = uextend.i32 v2
v7 = select v8, v5, v3 ; v5 = 1
return v7
}
full log are.
[abc.log](https://github.com/bytecodealliance/wasmtime/files/10788973/abc.log)
v7 = select v8, v5, v3 ; v5 = 1
This is wired. How come a `icmp eq` can become a `icmp sgt`.
yuyang-ok commented on issue #5839:
The code have been change from origin implementation.
I see anormalize_cmp_value
is wrong.
riscv64 can only compare int64 value.
normalize_cmp_value should do asinged extend
rather thanzero extend
on I8 and I16 .
yuyang-ok edited a comment on issue #5839:
The code have been change from origin implementation.
I see anormalize_cmp_value
is wrong.
riscv64 can only compare int64 value.
normalize_cmp_value should do asinged extend
rather thanzero extend
on I8 and I16 .
I seei32
implemented correctly.
yuyang-ok edited a comment on issue #5839:
The code have been change from origin implementation.
I see anormalize_cmp_value
is wrong.
riscv64 can only compare int64 value.
normalize_cmp_value should do asinged extend
rather thanzero extend
on I8 and I16 .
i32
implemented correctly.
yuyang-ok edited a comment on issue #5839:
This is because We should
signed extend
the value instead ofunsigned extend
jameysharp closed issue #5839:
:wave: Hey,
.clif
Test Casetest interpret test run set opt_level=speed target riscv64gc function %a(i8, i8) -> i32 { block0(v0: i8, v1: i8): v2 = icmp sle v0, v1 v3 = uextend.i32 v2 v4 = iconst.i32 0 v5 = iconst.i32 1 v6 = icmp.i32 eq v3, v4 ; v4 = 0 v7 = select v6, v5, v3 ; v5 = 1 return v7 } ; run: %a(20, -11) == 1
Steps to Reproduce
clif-util test ./the-above.clif
Expected Results
The test to pass
Actual Results
Running `qemu-riscv64 -L /usr/riscv64-linux-gnu -E LD_LIBRARY_PATH=/usr/riscv64-linux-gnu/lib /home/afonso/git/wasmtime/target/riscv64gc-unknown-linux-gnu/debug/clif-util test ./lmao.clif` ERROR cranelift_filetests::concurrent > FAIL: run FAIL ./lmao.clif: run Caused by: Failed test: run: %a(20, -11) == 1, actual: 0 1 tests Error: 1 failure
Versions and Environment
Cranelift version or commit: 1e6c94bec1a56a88ea3df518de0d073d26596580 (current main)
Operating system: Linux
Architecture: RISC-V
Extra Info
This testcase only fails with
opt_level=speed
, without it, it passes.<details>
<summary>Disassembly withopt_level=none
</summary>Disassembly of 72 bytes: 0: 13 18 85 03 slli a6, a0, 0x38 4: 13 58 88 43 srai a6, a6, 0x38 8: 13 9e 85 03 slli t3, a1, 0x38 c: 13 5e 8e 43 srai t3, t3, 0x38 10: 63 46 0e 01 blt t3, a6, 0xc 14: 93 02 10 00 addi t0, zero, 1 18: 6f 00 80 00 j 8 1c: 93 02 00 00 mv t0, zero 20: 13 fe f2 0f andi t3, t0, 0xff 24: 1b 07 0e 00 sext.w a4, t3 28: 13 08 00 00 mv a6, zero 2c: 9b 0e 08 00 sext.w t4, a6 30: 93 02 10 00 addi t0, zero, 1 34: 63 06 d7 01 beq a4, t4, 0xc 38: 13 65 0e 00 ori a0, t3, 0 3c: 6f 00 80 00 j 8 40: 13 e5 02 00 ori a0, t0, 0 44: 67 80 00 00 ret
</details>
<details>
<summary>Disassembly withopt_level=speed
</summary>Disassembly of 68 bytes: 0: 93 08 10 00 addi a7, zero, 1 4: 93 17 85 03 slli a5, a0, 0x38 8: 93 d7 87 43 srai a5, a5, 0x38 c: 13 9e 85 03 slli t3, a1, 0x38 10: 13 5e 8e 43 srai t3, t3, 0x38 14: 63 46 fe 00 blt t3, a5, 0xc 18: 93 0e 10 00 addi t4, zero, 1 1c: 6f 00 80 00 j 8 20: 93 0e 00 00 mv t4, zero 24: 13 fe fe 0f andi t3, t4, 0xff 28: 93 77 f5 0f andi a5, a0, 0xff 2c: 93 fe f5 0f andi t4, a1, 0xff 30: 63 c6 fe 00 blt t4, a5, 0xc 34: 13 65 0e 00 ori a0, t3, 0 38: 6f 00 80 00 j 8 3c: 13 e5 08 00 ori a0, a7, 0 40: 67 80 00 00 ret
</details>
cc: @yuyang-ok
Last updated: Dec 23 2024 at 13:07 UTC