Stream: git-wasmtime

Topic: wasmtime / issue #5526 Cranelift: Wrong result for `selec...

Wasmtime GitHub notifications bot (Jan 05 2023 at 11:40):

afonso360 labeled issue #5526:

:wave: Hey,

.clif Test Case

Sorry for the long test case, but I cannot minimize this further. Removing any function arguments / returns / stack_stores makes the test pass.

test interpret
test run
target riscv64

function %a(i128, i8, i8, i8, i16, i32, i8, i8, i64, i8) -> i8, i8, i8, i128, i8, i8, i64, i128, i8 system_v {
    ss0 = explicit_slot 90
    ss1 = explicit_slot 90
    ss2 = explicit_slot 90
    ss3 = explicit_slot 90
    ss4 = explicit_slot 126
    ss5 = explicit_slot 126
    ss6 = explicit_slot 126
    ss7 = explicit_slot 126

block0(v0: i128, v1: i8, v2: i8, v3: i8, v4: i16, v5: i32, v6: i8, v7: i8, v8: i64, v9: i8):
    v11 = iconst.i8 50
    v12 = iconst.i8 0
    v13 = iconst.i16 0
    v14 = iconst.i32 0
    v15 = iconst.i64 0
    v16 = uextend.i128 v15  ; v15 = 0
    stack_store v16, ss0
    stack_store v16, ss0+16
    stack_store v16, ss0+32
    stack_store v16, ss0+48
    stack_store v16, ss0+64
    stack_store v15, ss0+80  ; v15 = 0
    stack_store v13, ss0+88  ; v13 = 0
    stack_store v16, ss1
    stack_store v16, ss1+16
    stack_store v16, ss1+32
    stack_store v16, ss1+48
    stack_store v16, ss1+64
    stack_store v15, ss1+80  ; v15 = 0
    stack_store v13, ss1+88  ; v13 = 0
    stack_store v16, ss2
    stack_store v16, ss2+16
    stack_store v16, ss2+32
    stack_store v16, ss2+48
    stack_store v16, ss2+64
    stack_store v15, ss2+80  ; v15 = 0
    stack_store v13, ss2+88  ; v13 = 0
    stack_store v16, ss3
    stack_store v16, ss3+16
    stack_store v16, ss3+32
    stack_store v16, ss3+48
    stack_store v16, ss3+64
    stack_store v15, ss3+80  ; v15 = 0
    stack_store v13, ss3+88  ; v13 = 0
    stack_store v16, ss4
    stack_store v16, ss4+16
    stack_store v16, ss4+32
    stack_store v16, ss4+48
    stack_store v16, ss4+64
    stack_store v16, ss4+80
    stack_store v16, ss4+96
    stack_store v15, ss4+112  ; v15 = 0
    stack_store v14, ss4+120  ; v14 = 0
    stack_store v13, ss4+124  ; v13 = 0
    stack_store v16, ss5
    stack_store v16, ss5+16
    stack_store v16, ss5+32
    stack_store v16, ss5+48
    stack_store v16, ss5+64
    stack_store v16, ss5+80
    stack_store v16, ss5+96
    stack_store v15, ss5+112  ; v15 = 0
    stack_store v14, ss5+120  ; v14 = 0
    stack_store v13, ss5+124  ; v13 = 0
    stack_store v16, ss6
    stack_store v16, ss6+16
    stack_store v16, ss6+32
    stack_store v16, ss6+48
    stack_store v16, ss6+64
    stack_store v16, ss6+80
    stack_store v16, ss6+96
    stack_store v15, ss6+112  ; v15 = 0
    stack_store v14, ss6+120  ; v14 = 0
    stack_store v13, ss6+124  ; v13 = 0
    stack_store v16, ss7
    stack_store v16, ss7+16
    stack_store v16, ss7+32
    stack_store v16, ss7+48
    stack_store v16, ss7+64
    stack_store v16, ss7+80
    stack_store v16, ss7+96
    stack_store v15, ss7+112  ; v15 = 0
    stack_store v14, ss7+120  ; v14 = 0
    stack_store v13, ss7+124  ; v13 = 0


    v17 = select_spectre_guard v8, v0, v0
    v18 = isub v8, v8

    return v1, v3, v2, v17, v1, v1, v18, v17, v6
}

; run: %a(64324483005384539584200704, 0, 0, 95, 24415, 1600085839, 1, 0, 89294900846985228, 4) == [0, 95, 0, 64324483005384539584200704, 0, 0, 0, 64324483005384539584200704, 1]

Steps to Reproduce

• cargo run --target riscv64gc-unknown-linux-gnu -- test ./the-above.clif

Expected Results

The test to pass.

Actual Results

 ERROR cranelift_filetests::concurrent > FAIL: run
FAIL ./lmao.clif: run

Caused by:
    Failed test: run: %a(64324483005384539584200704, 0, 0, 95, 24415, 1600085839, 1, 0, 89294900846985228, 4) == [0, 95, 0, 64324483005384539584200704, 0, 0, 0, 64324483005384539584200704, 1], actual: [0, 95, 0, 71773119526705587960633590846666440704, 0, 0, 0, 71773119526705587960633590846666440704, 1]
1 tests
Error: 1 failure

Versions and Environment

Cranelift version or commit: main
Operating system: Linux
Architecture: riscv64

Extra Info

<details>
<summary>Disassembly:</summary>

Disassembly of 964 bytes:
   0:   13 01 01 ff             addi    sp, sp, -0x10
   4:   23 34 11 00             sd      ra, 8(sp)
   8:   23 30 81 00             sd      s0, 0(sp)
   c:   13 64 01 00             ori     s0, sp, 0
  10:   23 3c 91 ff             sd      s9, -8(sp)
  14:   13 01 01 c7             addi    sp, sp, -0x390
  18:   93 6c 07 00             ori     s9, a4, 0
  1c:   03 08 04 01             lb      a6, 0x10(s0)
  20:   03 3e 84 01             ld      t3, 0x18(s0)
  24:   83 02 04 02             lb      t0, 0x20(s0)
  28:   83 33 84 02             ld      t2, 0x28(s0)
  2c:   13 07 00 00             mv      a4, zero
  30:   93 07 00 00             mv      a5, zero
  34:   13 08 01 00             mv      a6, sp
  38:   23 30 e8 00             sd      a4, 0(a6)
  3c:   23 34 f8 00             sd      a5, 8(a6)
  40:   13 08 01 01             addi    a6, sp, 0x10
  44:   23 30 e8 00             sd      a4, 0(a6)
  48:   23 34 f8 00             sd      a5, 8(a6)
  4c:   93 0e 01 02             addi    t4, sp, 0x20
  50:   23 b0 ee 00             sd      a4, 0(t4)
  54:   23 b4 fe 00             sd      a5, 8(t4)
  58:   93 0e 01 03             addi    t4, sp, 0x30
  5c:   23 b0 ee 00             sd      a4, 0(t4)
  60:   23 b4 fe 00             sd      a5, 8(t4)
  64:   13 03 01 04             addi    t1, sp, 0x40
  68:   23 30 e3 00             sd      a4, 0(t1)
  6c:   23 34 f3 00             sd      a5, 8(t1)
  70:   13 08 01 05             addi    a6, sp, 0x50
  74:   93 0e 00 00             mv      t4, zero
  78:   23 30 d8 01             sd      t4, 0(a6)
  7c:   13 08 81 05             addi    a6, sp, 0x58
  80:   93 0e 00 00             mv      t4, zero
  84:   23 10 d8 01             sh      t4, 0(a6)
  88:   13 08 01 06             addi    a6, sp, 0x60
  8c:   23 30 e8 00             sd      a4, 0(a6)
  90:   23 34 f8 00             sd      a5, 8(a6)
  94:   13 08 01 07             addi    a6, sp, 0x70
  98:   23 30 e8 00             sd      a4, 0(a6)
  9c:   23 34 f8 00             sd      a5, 8(a6)
  a0:   13 08 01 08             addi    a6, sp, 0x80
  a4:   23 30 e8 00             sd      a4, 0(a6)
  a8:   23 34 f8 00             sd      a5, 8(a6)
  ac:   93 0e 01 09             addi    t4, sp, 0x90
  b0:   23 b0 ee 00             sd      a4, 0(t4)
  b4:   23 b4 fe 00             sd      a5, 8(t4)
  b8:   93 02 01 0a             addi    t0, sp, 0xa0
  bc:   23 b0 e2 00             sd      a4, 0(t0)
  c0:   23 b4 f2 00             sd      a5, 8(t0)
  c4:   13 08 01 0b             addi    a6, sp, 0xb0
  c8:   93 0e 00 00             mv      t4, zero
  cc:   23 30 d8 01             sd      t4, 0(a6)
  d0:   13 08 81 0b             addi    a6, sp, 0xb8
  d4:   93 0e 00 00             mv      t4, zero
  d8:   23 10 d8 01             sh      t4, 0(a6)
  dc:   13 08 01 0c             addi    a6, sp, 0xc0
  e0:   23 30 e8 00             sd      a4, 0(a6)
  e4:   23 34 f8 00             sd      a5, 8(a6)
  e8:   13 08 01 0d             addi    a6, sp, 0xd0
  ec:   23 30 e8 00             sd      a4, 0(a6)
  f0:   23 34 f8 00             sd      a5, 8(a6)
  f4:   13 08 01 0e             addi    a6, sp, 0xe0
  f8:   23 30 e8 00             sd      a4, 0(a6)
  fc:   23 34 f8 00             sd      a5, 8(a6)
 100:   93 0e 01 0f             addi    t4, sp, 0xf0
 104:   23 b0 ee 00             sd      a4, 0(t4)
 108:   23 b4 fe 00             sd      a5, 8(t4)
 10c:   93 0e 01 10             addi    t4, sp, 0x100
 110:   23 b0 ee 00             sd      a4, 0(t4)
 114:   23 b4 fe 00             sd      a5, 8(t4)
 118:   13 03 01 11             addi    t1, sp, 0x110
 11c:   13 08 00 00             mv      a6, zero
 120:   23 30 03 01             sd      a6, 0(t1)
 124:   13 08 81 11             addi    a6, sp, 0x118
 128:   93 0e 00 00             mv      t4, zero
 12c:   23 10 d8 01             sh      t4, 0(a6)
 130:   13 08 01 12             addi    a6, sp, 0x120
 134:   23 30 e8 00             sd      a4, 0(a6)
 138:   23 34 f8 00             sd      a5, 8(a6)
 13c:   13 08 01 13             addi    a6, sp, 0x130
 140:   23 30 e8 00             sd      a4, 0(a6)
 144:   23 34 f8 00             sd      a5, 8(a6)
 148:   13 08 01 14             addi    a6, sp, 0x140
 14c:   23 30 e8 00             sd      a4, 0(a6)
 150:   23 34 f8 00             sd      a5, 8(a6)
 154:   13 08 01 15             addi    a6, sp, 0x150
 158:   23 30 e8 00             sd      a4, 0(a6)
 15c:   23 34 f8 00             sd      a5, 8(a6)
 160:   93 0e 01 16             addi    t4, sp, 0x160
 164:   23 b0 ee 00             sd      a4, 0(t4)
 168:   23 b4 fe 00             sd      a5, 8(t4)
 16c:   93 02 01 17             addi    t0, sp, 0x170
 170:   13 03 00 00             mv      t1, zero
 174:   23 b0 62 00             sd      t1, 0(t0)
 178:   13 03 81 17             addi    t1, sp, 0x178
 17c:   13 08 00 00             mv      a6, zero
 180:   23 10 03 01             sh      a6, 0(t1)
 184:   13 08 01 18             addi    a6, sp, 0x180
 188:   23 30 e8 00             sd      a4, 0(a6)
 18c:   23 34 f8 00             sd      a5, 8(a6)
 190:   13 08 01 19             addi    a6, sp, 0x190
 194:   23 30 e8 00             sd      a4, 0(a6)
 198:   23 34 f8 00             sd      a5, 8(a6)
 19c:   13 08 01 1a             addi    a6, sp, 0x1a0
 1a0:   23 30 e8 00             sd      a4, 0(a6)
 1a4:   23 34 f8 00             sd      a5, 8(a6)
 1a8:   13 08 01 1b             addi    a6, sp, 0x1b0
 1ac:   23 30 e8 00             sd      a4, 0(a6)
 1b0:   23 34 f8 00             sd      a5, 8(a6)
 1b4:   93 0e 01 1c             addi    t4, sp, 0x1c0
 1b8:   2
[message truncated]

Wasmtime GitHub notifications bot (Jan 05 2023 at 11:40):

afonso360 opened issue #5526:

:wave: Hey,

.clif Test Case

Sorry for the long test case, but I cannot minimize this further. Removing any function arguments / returns / stack_stores makes the test pass.

test interpret
test run
target riscv64

function %a(i128, i8, i8, i8, i16, i32, i8, i8, i64, i8) -> i8, i8, i8, i128, i8, i8, i64, i128, i8 system_v {
    ss0 = explicit_slot 90
    ss1 = explicit_slot 90
    ss2 = explicit_slot 90
    ss3 = explicit_slot 90
    ss4 = explicit_slot 126
    ss5 = explicit_slot 126
    ss6 = explicit_slot 126
    ss7 = explicit_slot 126

block0(v0: i128, v1: i8, v2: i8, v3: i8, v4: i16, v5: i32, v6: i8, v7: i8, v8: i64, v9: i8):
    v11 = iconst.i8 50
    v12 = iconst.i8 0
    v13 = iconst.i16 0
    v14 = iconst.i32 0
    v15 = iconst.i64 0
    v16 = uextend.i128 v15  ; v15 = 0
    stack_store v16, ss0
    stack_store v16, ss0+16
    stack_store v16, ss0+32
    stack_store v16, ss0+48
    stack_store v16, ss0+64
    stack_store v15, ss0+80  ; v15 = 0
    stack_store v13, ss0+88  ; v13 = 0
    stack_store v16, ss1
    stack_store v16, ss1+16
    stack_store v16, ss1+32
    stack_store v16, ss1+48
    stack_store v16, ss1+64
    stack_store v15, ss1+80  ; v15 = 0
    stack_store v13, ss1+88  ; v13 = 0
    stack_store v16, ss2
    stack_store v16, ss2+16
    stack_store v16, ss2+32
    stack_store v16, ss2+48
    stack_store v16, ss2+64
    stack_store v15, ss2+80  ; v15 = 0
    stack_store v13, ss2+88  ; v13 = 0
    stack_store v16, ss3
    stack_store v16, ss3+16
    stack_store v16, ss3+32
    stack_store v16, ss3+48
    stack_store v16, ss3+64
    stack_store v15, ss3+80  ; v15 = 0
    stack_store v13, ss3+88  ; v13 = 0
    stack_store v16, ss4
    stack_store v16, ss4+16
    stack_store v16, ss4+32
    stack_store v16, ss4+48
    stack_store v16, ss4+64
    stack_store v16, ss4+80
    stack_store v16, ss4+96
    stack_store v15, ss4+112  ; v15 = 0
    stack_store v14, ss4+120  ; v14 = 0
    stack_store v13, ss4+124  ; v13 = 0
    stack_store v16, ss5
    stack_store v16, ss5+16
    stack_store v16, ss5+32
    stack_store v16, ss5+48
    stack_store v16, ss5+64
    stack_store v16, ss5+80
    stack_store v16, ss5+96
    stack_store v15, ss5+112  ; v15 = 0
    stack_store v14, ss5+120  ; v14 = 0
    stack_store v13, ss5+124  ; v13 = 0
    stack_store v16, ss6
    stack_store v16, ss6+16
    stack_store v16, ss6+32
    stack_store v16, ss6+48
    stack_store v16, ss6+64
    stack_store v16, ss6+80
    stack_store v16, ss6+96
    stack_store v15, ss6+112  ; v15 = 0
    stack_store v14, ss6+120  ; v14 = 0
    stack_store v13, ss6+124  ; v13 = 0
    stack_store v16, ss7
    stack_store v16, ss7+16
    stack_store v16, ss7+32
    stack_store v16, ss7+48
    stack_store v16, ss7+64
    stack_store v16, ss7+80
    stack_store v16, ss7+96
    stack_store v15, ss7+112  ; v15 = 0
    stack_store v14, ss7+120  ; v14 = 0
    stack_store v13, ss7+124  ; v13 = 0


    v17 = select_spectre_guard v8, v0, v0
    v18 = isub v8, v8

    return v1, v3, v2, v17, v1, v1, v18, v17, v6
}

; run: %a(64324483005384539584200704, 0, 0, 95, 24415, 1600085839, 1, 0, 89294900846985228, 4) == [0, 95, 0, 64324483005384539584200704, 0, 0, 0, 64324483005384539584200704, 1]

Steps to Reproduce

• cargo run --target riscv64gc-unknown-linux-gnu -- test ./the-above.clif

Expected Results

The test to pass.

Actual Results

 ERROR cranelift_filetests::concurrent > FAIL: run
FAIL ./lmao.clif: run

Caused by:
    Failed test: run: %a(64324483005384539584200704, 0, 0, 95, 24415, 1600085839, 1, 0, 89294900846985228, 4) == [0, 95, 0, 64324483005384539584200704, 0, 0, 0, 64324483005384539584200704, 1], actual: [0, 95, 0, 71773119526705587960633590846666440704, 0, 0, 0, 71773119526705587960633590846666440704, 1]
1 tests
Error: 1 failure

Versions and Environment

Cranelift version or commit: main
Operating system: Linux
Architecture: riscv64

Extra Info

<details>
<summary>Disassembly:</summary>

Disassembly of 964 bytes:
   0:   13 01 01 ff             addi    sp, sp, -0x10
   4:   23 34 11 00             sd      ra, 8(sp)
   8:   23 30 81 00             sd      s0, 0(sp)
   c:   13 64 01 00             ori     s0, sp, 0
  10:   23 3c 91 ff             sd      s9, -8(sp)
  14:   13 01 01 c7             addi    sp, sp, -0x390
  18:   93 6c 07 00             ori     s9, a4, 0
  1c:   03 08 04 01             lb      a6, 0x10(s0)
  20:   03 3e 84 01             ld      t3, 0x18(s0)
  24:   83 02 04 02             lb      t0, 0x20(s0)
  28:   83 33 84 02             ld      t2, 0x28(s0)
  2c:   13 07 00 00             mv      a4, zero
  30:   93 07 00 00             mv      a5, zero
  34:   13 08 01 00             mv      a6, sp
  38:   23 30 e8 00             sd      a4, 0(a6)
  3c:   23 34 f8 00             sd      a5, 8(a6)
  40:   13 08 01 01             addi    a6, sp, 0x10
  44:   23 30 e8 00             sd      a4, 0(a6)
  48:   23 34 f8 00             sd      a5, 8(a6)
  4c:   93 0e 01 02             addi    t4, sp, 0x20
  50:   23 b0 ee 00             sd      a4, 0(t4)
  54:   23 b4 fe 00             sd      a5, 8(t4)
  58:   93 0e 01 03             addi    t4, sp, 0x30
  5c:   23 b0 ee 00             sd      a4, 0(t4)
  60:   23 b4 fe 00             sd      a5, 8(t4)
  64:   13 03 01 04             addi    t1, sp, 0x40
  68:   23 30 e3 00             sd      a4, 0(t1)
  6c:   23 34 f3 00             sd      a5, 8(t1)
  70:   13 08 01 05             addi    a6, sp, 0x50
  74:   93 0e 00 00             mv      t4, zero
  78:   23 30 d8 01             sd      t4, 0(a6)
  7c:   13 08 81 05             addi    a6, sp, 0x58
  80:   93 0e 00 00             mv      t4, zero
  84:   23 10 d8 01             sh      t4, 0(a6)
  88:   13 08 01 06             addi    a6, sp, 0x60
  8c:   23 30 e8 00             sd      a4, 0(a6)
  90:   23 34 f8 00             sd      a5, 8(a6)
  94:   13 08 01 07             addi    a6, sp, 0x70
  98:   23 30 e8 00             sd      a4, 0(a6)
  9c:   23 34 f8 00             sd      a5, 8(a6)
  a0:   13 08 01 08             addi    a6, sp, 0x80
  a4:   23 30 e8 00             sd      a4, 0(a6)
  a8:   23 34 f8 00             sd      a5, 8(a6)
  ac:   93 0e 01 09             addi    t4, sp, 0x90
  b0:   23 b0 ee 00             sd      a4, 0(t4)
  b4:   23 b4 fe 00             sd      a5, 8(t4)
  b8:   93 02 01 0a             addi    t0, sp, 0xa0
  bc:   23 b0 e2 00             sd      a4, 0(t0)
  c0:   23 b4 f2 00             sd      a5, 8(t0)
  c4:   13 08 01 0b             addi    a6, sp, 0xb0
  c8:   93 0e 00 00             mv      t4, zero
  cc:   23 30 d8 01             sd      t4, 0(a6)
  d0:   13 08 81 0b             addi    a6, sp, 0xb8
  d4:   93 0e 00 00             mv      t4, zero
  d8:   23 10 d8 01             sh      t4, 0(a6)
  dc:   13 08 01 0c             addi    a6, sp, 0xc0
  e0:   23 30 e8 00             sd      a4, 0(a6)
  e4:   23 34 f8 00             sd      a5, 8(a6)
  e8:   13 08 01 0d             addi    a6, sp, 0xd0
  ec:   23 30 e8 00             sd      a4, 0(a6)
  f0:   23 34 f8 00             sd      a5, 8(a6)
  f4:   13 08 01 0e             addi    a6, sp, 0xe0
  f8:   23 30 e8 00             sd      a4, 0(a6)
  fc:   23 34 f8 00             sd      a5, 8(a6)
 100:   93 0e 01 0f             addi    t4, sp, 0xf0
 104:   23 b0 ee 00             sd      a4, 0(t4)
 108:   23 b4 fe 00             sd      a5, 8(t4)
 10c:   93 0e 01 10             addi    t4, sp, 0x100
 110:   23 b0 ee 00             sd      a4, 0(t4)
 114:   23 b4 fe 00             sd      a5, 8(t4)
 118:   13 03 01 11             addi    t1, sp, 0x110
 11c:   13 08 00 00             mv      a6, zero
 120:   23 30 03 01             sd      a6, 0(t1)
 124:   13 08 81 11             addi    a6, sp, 0x118
 128:   93 0e 00 00             mv      t4, zero
 12c:   23 10 d8 01             sh      t4, 0(a6)
 130:   13 08 01 12             addi    a6, sp, 0x120
 134:   23 30 e8 00             sd      a4, 0(a6)
 138:   23 34 f8 00             sd      a5, 8(a6)
 13c:   13 08 01 13             addi    a6, sp, 0x130
 140:   23 30 e8 00             sd      a4, 0(a6)
 144:   23 34 f8 00             sd      a5, 8(a6)
 148:   13 08 01 14             addi    a6, sp, 0x140
 14c:   23 30 e8 00             sd      a4, 0(a6)
 150:   23 34 f8 00             sd      a5, 8(a6)
 154:   13 08 01 15             addi    a6, sp, 0x150
 158:   23 30 e8 00             sd      a4, 0(a6)
 15c:   23 34 f8 00             sd      a5, 8(a6)
 160:   93 0e 01 16             addi    t4, sp, 0x160
 164:   23 b0 ee 00             sd      a4, 0(t4)
 168:   23 b4 fe 00             sd      a5, 8(t4)
 16c:   93 02 01 17             addi    t0, sp, 0x170
 170:   13 03 00 00             mv      t1, zero
 174:   23 b0 62 00             sd      t1, 0(t0)
 178:   13 03 81 17             addi    t1, sp, 0x178
 17c:   13 08 00 00             mv      a6, zero
 180:   23 10 03 01             sh      a6, 0(t1)
 184:   13 08 01 18             addi    a6, sp, 0x180
 188:   23 30 e8 00             sd      a4, 0(a6)
 18c:   23 34 f8 00             sd      a5, 8(a6)
 190:   13 08 01 19             addi    a6, sp, 0x190
 194:   23 30 e8 00             sd      a4, 0(a6)
 198:   23 34 f8 00             sd      a5, 8(a6)
 19c:   13 08 01 1a             addi    a6, sp, 0x1a0
 1a0:   23 30 e8 00             sd      a4, 0(a6)
 1a4:   23 34 f8 00             sd      a5, 8(a6)
 1a8:   13 08 01 1b             addi    a6, sp, 0x1b0
 1ac:   23 30 e8 00             sd      a4, 0(a6)
 1b0:   23 34 f8 00             sd      a5, 8(a6)
 1b4:   93 0e 01 1c             addi    t4, sp, 0x1c0
 1b8:   23
[message truncated]

Wasmtime GitHub notifications bot (Jan 05 2023 at 11:40):

afonso360 labeled issue #5526:

:wave: Hey,

.clif Test Case

Sorry for the long test case, but I cannot minimize this further. Removing any function arguments / returns / stack_stores makes the test pass.

test interpret
test run
target riscv64

function %a(i128, i8, i8, i8, i16, i32, i8, i8, i64, i8) -> i8, i8, i8, i128, i8, i8, i64, i128, i8 system_v {
    ss0 = explicit_slot 90
    ss1 = explicit_slot 90
    ss2 = explicit_slot 90
    ss3 = explicit_slot 90
    ss4 = explicit_slot 126
    ss5 = explicit_slot 126
    ss6 = explicit_slot 126
    ss7 = explicit_slot 126

block0(v0: i128, v1: i8, v2: i8, v3: i8, v4: i16, v5: i32, v6: i8, v7: i8, v8: i64, v9: i8):
    v11 = iconst.i8 50
    v12 = iconst.i8 0
    v13 = iconst.i16 0
    v14 = iconst.i32 0
    v15 = iconst.i64 0
    v16 = uextend.i128 v15  ; v15 = 0
    stack_store v16, ss0
    stack_store v16, ss0+16
    stack_store v16, ss0+32
    stack_store v16, ss0+48
    stack_store v16, ss0+64
    stack_store v15, ss0+80  ; v15 = 0
    stack_store v13, ss0+88  ; v13 = 0
    stack_store v16, ss1
    stack_store v16, ss1+16
    stack_store v16, ss1+32
    stack_store v16, ss1+48
    stack_store v16, ss1+64
    stack_store v15, ss1+80  ; v15 = 0
    stack_store v13, ss1+88  ; v13 = 0
    stack_store v16, ss2
    stack_store v16, ss2+16
    stack_store v16, ss2+32
    stack_store v16, ss2+48
    stack_store v16, ss2+64
    stack_store v15, ss2+80  ; v15 = 0
    stack_store v13, ss2+88  ; v13 = 0
    stack_store v16, ss3
    stack_store v16, ss3+16
    stack_store v16, ss3+32
    stack_store v16, ss3+48
    stack_store v16, ss3+64
    stack_store v15, ss3+80  ; v15 = 0
    stack_store v13, ss3+88  ; v13 = 0
    stack_store v16, ss4
    stack_store v16, ss4+16
    stack_store v16, ss4+32
    stack_store v16, ss4+48
    stack_store v16, ss4+64
    stack_store v16, ss4+80
    stack_store v16, ss4+96
    stack_store v15, ss4+112  ; v15 = 0
    stack_store v14, ss4+120  ; v14 = 0
    stack_store v13, ss4+124  ; v13 = 0
    stack_store v16, ss5
    stack_store v16, ss5+16
    stack_store v16, ss5+32
    stack_store v16, ss5+48
    stack_store v16, ss5+64
    stack_store v16, ss5+80
    stack_store v16, ss5+96
    stack_store v15, ss5+112  ; v15 = 0
    stack_store v14, ss5+120  ; v14 = 0
    stack_store v13, ss5+124  ; v13 = 0
    stack_store v16, ss6
    stack_store v16, ss6+16
    stack_store v16, ss6+32
    stack_store v16, ss6+48
    stack_store v16, ss6+64
    stack_store v16, ss6+80
    stack_store v16, ss6+96
    stack_store v15, ss6+112  ; v15 = 0
    stack_store v14, ss6+120  ; v14 = 0
    stack_store v13, ss6+124  ; v13 = 0
    stack_store v16, ss7
    stack_store v16, ss7+16
    stack_store v16, ss7+32
    stack_store v16, ss7+48
    stack_store v16, ss7+64
    stack_store v16, ss7+80
    stack_store v16, ss7+96
    stack_store v15, ss7+112  ; v15 = 0
    stack_store v14, ss7+120  ; v14 = 0
    stack_store v13, ss7+124  ; v13 = 0


    v17 = select_spectre_guard v8, v0, v0
    v18 = isub v8, v8

    return v1, v3, v2, v17, v1, v1, v18, v17, v6
}

; run: %a(64324483005384539584200704, 0, 0, 95, 24415, 1600085839, 1, 0, 89294900846985228, 4) == [0, 95, 0, 64324483005384539584200704, 0, 0, 0, 64324483005384539584200704, 1]

Steps to Reproduce

• cargo run --target riscv64gc-unknown-linux-gnu -- test ./the-above.clif

Expected Results

The test to pass.

Actual Results

 ERROR cranelift_filetests::concurrent > FAIL: run
FAIL ./lmao.clif: run

Caused by:
    Failed test: run: %a(64324483005384539584200704, 0, 0, 95, 24415, 1600085839, 1, 0, 89294900846985228, 4) == [0, 95, 0, 64324483005384539584200704, 0, 0, 0, 64324483005384539584200704, 1], actual: [0, 95, 0, 71773119526705587960633590846666440704, 0, 0, 0, 71773119526705587960633590846666440704, 1]
1 tests
Error: 1 failure

Versions and Environment

Cranelift version or commit: main
Operating system: Linux
Architecture: riscv64

Extra Info

<details>
<summary>Disassembly:</summary>

Disassembly of 964 bytes:
   0:   13 01 01 ff             addi    sp, sp, -0x10
   4:   23 34 11 00             sd      ra, 8(sp)
   8:   23 30 81 00             sd      s0, 0(sp)
   c:   13 64 01 00             ori     s0, sp, 0
  10:   23 3c 91 ff             sd      s9, -8(sp)
  14:   13 01 01 c7             addi    sp, sp, -0x390
  18:   93 6c 07 00             ori     s9, a4, 0
  1c:   03 08 04 01             lb      a6, 0x10(s0)
  20:   03 3e 84 01             ld      t3, 0x18(s0)
  24:   83 02 04 02             lb      t0, 0x20(s0)
  28:   83 33 84 02             ld      t2, 0x28(s0)
  2c:   13 07 00 00             mv      a4, zero
  30:   93 07 00 00             mv      a5, zero
  34:   13 08 01 00             mv      a6, sp
  38:   23 30 e8 00             sd      a4, 0(a6)
  3c:   23 34 f8 00             sd      a5, 8(a6)
  40:   13 08 01 01             addi    a6, sp, 0x10
  44:   23 30 e8 00             sd      a4, 0(a6)
  48:   23 34 f8 00             sd      a5, 8(a6)
  4c:   93 0e 01 02             addi    t4, sp, 0x20
  50:   23 b0 ee 00             sd      a4, 0(t4)
  54:   23 b4 fe 00             sd      a5, 8(t4)
  58:   93 0e 01 03             addi    t4, sp, 0x30
  5c:   23 b0 ee 00             sd      a4, 0(t4)
  60:   23 b4 fe 00             sd      a5, 8(t4)
  64:   13 03 01 04             addi    t1, sp, 0x40
  68:   23 30 e3 00             sd      a4, 0(t1)
  6c:   23 34 f3 00             sd      a5, 8(t1)
  70:   13 08 01 05             addi    a6, sp, 0x50
  74:   93 0e 00 00             mv      t4, zero
  78:   23 30 d8 01             sd      t4, 0(a6)
  7c:   13 08 81 05             addi    a6, sp, 0x58
  80:   93 0e 00 00             mv      t4, zero
  84:   23 10 d8 01             sh      t4, 0(a6)
  88:   13 08 01 06             addi    a6, sp, 0x60
  8c:   23 30 e8 00             sd      a4, 0(a6)
  90:   23 34 f8 00             sd      a5, 8(a6)
  94:   13 08 01 07             addi    a6, sp, 0x70
  98:   23 30 e8 00             sd      a4, 0(a6)
  9c:   23 34 f8 00             sd      a5, 8(a6)
  a0:   13 08 01 08             addi    a6, sp, 0x80
  a4:   23 30 e8 00             sd      a4, 0(a6)
  a8:   23 34 f8 00             sd      a5, 8(a6)
  ac:   93 0e 01 09             addi    t4, sp, 0x90
  b0:   23 b0 ee 00             sd      a4, 0(t4)
  b4:   23 b4 fe 00             sd      a5, 8(t4)
  b8:   93 02 01 0a             addi    t0, sp, 0xa0
  bc:   23 b0 e2 00             sd      a4, 0(t0)
  c0:   23 b4 f2 00             sd      a5, 8(t0)
  c4:   13 08 01 0b             addi    a6, sp, 0xb0
  c8:   93 0e 00 00             mv      t4, zero
  cc:   23 30 d8 01             sd      t4, 0(a6)
  d0:   13 08 81 0b             addi    a6, sp, 0xb8
  d4:   93 0e 00 00             mv      t4, zero
  d8:   23 10 d8 01             sh      t4, 0(a6)
  dc:   13 08 01 0c             addi    a6, sp, 0xc0
  e0:   23 30 e8 00             sd      a4, 0(a6)
  e4:   23 34 f8 00             sd      a5, 8(a6)
  e8:   13 08 01 0d             addi    a6, sp, 0xd0
  ec:   23 30 e8 00             sd      a4, 0(a6)
  f0:   23 34 f8 00             sd      a5, 8(a6)
  f4:   13 08 01 0e             addi    a6, sp, 0xe0
  f8:   23 30 e8 00             sd      a4, 0(a6)
  fc:   23 34 f8 00             sd      a5, 8(a6)
 100:   93 0e 01 0f             addi    t4, sp, 0xf0
 104:   23 b0 ee 00             sd      a4, 0(t4)
 108:   23 b4 fe 00             sd      a5, 8(t4)
 10c:   93 0e 01 10             addi    t4, sp, 0x100
 110:   23 b0 ee 00             sd      a4, 0(t4)
 114:   23 b4 fe 00             sd      a5, 8(t4)
 118:   13 03 01 11             addi    t1, sp, 0x110
 11c:   13 08 00 00             mv      a6, zero
 120:   23 30 03 01             sd      a6, 0(t1)
 124:   13 08 81 11             addi    a6, sp, 0x118
 128:   93 0e 00 00             mv      t4, zero
 12c:   23 10 d8 01             sh      t4, 0(a6)
 130:   13 08 01 12             addi    a6, sp, 0x120
 134:   23 30 e8 00             sd      a4, 0(a6)
 138:   23 34 f8 00             sd      a5, 8(a6)
 13c:   13 08 01 13             addi    a6, sp, 0x130
 140:   23 30 e8 00             sd      a4, 0(a6)
 144:   23 34 f8 00             sd      a5, 8(a6)
 148:   13 08 01 14             addi    a6, sp, 0x140
 14c:   23 30 e8 00             sd      a4, 0(a6)
 150:   23 34 f8 00             sd      a5, 8(a6)
 154:   13 08 01 15             addi    a6, sp, 0x150
 158:   23 30 e8 00             sd      a4, 0(a6)
 15c:   23 34 f8 00             sd      a5, 8(a6)
 160:   93 0e 01 16             addi    t4, sp, 0x160
 164:   23 b0 ee 00             sd      a4, 0(t4)
 168:   23 b4 fe 00             sd      a5, 8(t4)
 16c:   93 02 01 17             addi    t0, sp, 0x170
 170:   13 03 00 00             mv      t1, zero
 174:   23 b0 62 00             sd      t1, 0(t0)
 178:   13 03 81 17             addi    t1, sp, 0x178
 17c:   13 08 00 00             mv      a6, zero
 180:   23 10 03 01             sh      a6, 0(t1)
 184:   13 08 01 18             addi    a6, sp, 0x180
 188:   23 30 e8 00             sd      a4, 0(a6)
 18c:   23 34 f8 00             sd      a5, 8(a6)
 190:   13 08 01 19             addi    a6, sp, 0x190
 194:   23 30 e8 00             sd      a4, 0(a6)
 198:   23 34 f8 00             sd      a5, 8(a6)
 19c:   13 08 01 1a             addi    a6, sp, 0x1a0
 1a0:   23 30 e8 00             sd      a4, 0(a6)
 1a4:   23 34 f8 00             sd      a5, 8(a6)
 1a8:   13 08 01 1b             addi    a6, sp, 0x1b0
 1ac:   23 30 e8 00             sd      a4, 0(a6)
 1b0:   23 34 f8 00             sd      a5, 8(a6)
 1b4:   93 0e 01 1c             addi    t4, sp, 0x1c0
 1b8:   2
[message truncated]