wasmtime / issue #5500 Cranelift: Register allocation err... · git-wasmtime

Stream: git-wasmtime

Topic: wasmtime / issue #5500 Cranelift: Register allocation err...

Wasmtime GitHub notifications bot (Dec 30 2022 at 17:56):

afonso360 labeled issue #5500:

:wave: Hey,

`.clif` Test Case

test compile
target riscv64

function u1:0() {
block0:
    v0 = f64const 0.0
    v1 = fcmp eq v0, v0
    brz v1, block1
    jump block1

block1:
    return
}

Steps to Reproduce

cargo run -- compile -D --target riscv64 ./the-above.clif

Expected Results

The file to compile

Actual Results

ERROR cranelift_codegen::machinst::compile > Register allocation error for vcode
VCode {
  Entry block: 0
Block 0:
    (original IR block: block0)
    (successor: Block 1)
    (successor: Block 2)
    (instruction range: 0 .. 7)
  Inst 0: li v131,0
  Inst 1: fmv.d.x v130,v131
  Inst 2: li v133,0
  Inst 3: fmv.d.x v132,v133
  Inst 4: feq.d v134,v130,v132
  Inst 5: beq v134,zero,taken(label1),not_taken(0)
  Inst 6: j label2
Block 1:
    (successor: Block 3)
    (instruction range: 7 .. 8)
  Inst 7: j label3
Block 2:
    (successor: Block 3)
    (instruction range: 8 .. 9)
  Inst 8: j label3
Block 3:
    (original IR block: block1)
    (instruction range: 9 .. 10)
  Inst 9: ret
}

Error: BB(Block(0))
CLIF for error:
function u1:0() fast {
block0:
    v0 = f64const 0.0
    v1 = fcmp eq v0, v0  ; v0 = 0.0, v0 = 0.0
    brz v1, block1
    jump block1

block1:
    return
}

thread 'main' panicked at 'register allocation: BB(Block(0))', cranelift/codegen/src/machinst/compile.rs:67:14

Versions and Environment

Cranelift version or commit: main
Operating system: Linux
Architecture: riscv64

Extra Info

Changing the fcmp condition to uno instead of eq gets a slightly better error message.

 ERROR cranelift_codegen::machinst::compile > Register allocation error for vcode
VCode {
  Entry block: 0
Block 0:
    (original IR block: block0)
    (successor: Block 1)
    (successor: Block 2)
    (instruction range: 0 .. 9)
  Inst 0: li v131,0
  Inst 1: fmv.d.x v130,v131
  Inst 2: li v133,0
  Inst 3: fmv.d.x v132,v133
  Inst 4: fle.d v134,v132,v130
  Inst 5: bne v134,zero,taken(label1),not_taken(0)
  Inst 6: flt.d v134,v130,v132
  Inst 7: bne v134,zero,taken(label1),not_taken(0)
  Inst 8: j label2
Block 1:
    (successor: Block 3)
    (instruction range: 9 .. 10)
  Inst 9: j label3
Block 2:
    (successor: Block 3)
    (instruction range: 10 .. 11)
  Inst 10: j label3
Block 3:
    (original IR block: block1)
    (instruction range: 11 .. 12)
  Inst 11: ret
}

Error: SSA(VReg(vreg = 134, class = Int), Inst(6))
CLIF for error:
function u1:0() fast {
block0:
    v0 = f64const 0.0
    v1 = fcmp uno v0, v0  ; v0 = 0.0, v0 = 0.0
    brz v1, block1
    jump block1

block1:
    return
}

thread 'main' panicked at 'register allocation: SSA(VReg(vreg = 134, class = Int), Inst(6))', cranelift/codegen/src/machinst/compile.rs:67:14

Wasmtime GitHub notifications bot (Dec 30 2022 at 17:56):

afonso360 labeled issue #5500:

:wave: Hey,

`.clif` Test Case

test compile
target riscv64

function u1:0() {
block0:
    v0 = f64const 0.0
    v1 = fcmp eq v0, v0
    brz v1, block1
    jump block1

block1:
    return
}

Steps to Reproduce

cargo run -- compile -D --target riscv64 ./the-above.clif

Expected Results

The file to compile

Actual Results

ERROR cranelift_codegen::machinst::compile > Register allocation error for vcode
VCode {
  Entry block: 0
Block 0:
    (original IR block: block0)
    (successor: Block 1)
    (successor: Block 2)
    (instruction range: 0 .. 7)
  Inst 0: li v131,0
  Inst 1: fmv.d.x v130,v131
  Inst 2: li v133,0
  Inst 3: fmv.d.x v132,v133
  Inst 4: feq.d v134,v130,v132
  Inst 5: beq v134,zero,taken(label1),not_taken(0)
  Inst 6: j label2
Block 1:
    (successor: Block 3)
    (instruction range: 7 .. 8)
  Inst 7: j label3
Block 2:
    (successor: Block 3)
    (instruction range: 8 .. 9)
  Inst 8: j label3
Block 3:
    (original IR block: block1)
    (instruction range: 9 .. 10)
  Inst 9: ret
}

Error: BB(Block(0))
CLIF for error:
function u1:0() fast {
block0:
    v0 = f64const 0.0
    v1 = fcmp eq v0, v0  ; v0 = 0.0, v0 = 0.0
    brz v1, block1
    jump block1

block1:
    return
}

thread 'main' panicked at 'register allocation: BB(Block(0))', cranelift/codegen/src/machinst/compile.rs:67:14

Versions and Environment

Cranelift version or commit: main
Operating system: Linux
Architecture: riscv64

Extra Info

Changing the fcmp condition to uno instead of eq gets a slightly better error message.

 ERROR cranelift_codegen::machinst::compile > Register allocation error for vcode
VCode {
  Entry block: 0
Block 0:
    (original IR block: block0)
    (successor: Block 1)
    (successor: Block 2)
    (instruction range: 0 .. 9)
  Inst 0: li v131,0
  Inst 1: fmv.d.x v130,v131
  Inst 2: li v133,0
  Inst 3: fmv.d.x v132,v133
  Inst 4: fle.d v134,v132,v130
  Inst 5: bne v134,zero,taken(label1),not_taken(0)
  Inst 6: flt.d v134,v130,v132
  Inst 7: bne v134,zero,taken(label1),not_taken(0)
  Inst 8: j label2
Block 1:
    (successor: Block 3)
    (instruction range: 9 .. 10)
  Inst 9: j label3
Block 2:
    (successor: Block 3)
    (instruction range: 10 .. 11)
  Inst 10: j label3
Block 3:
    (original IR block: block1)
    (instruction range: 11 .. 12)
  Inst 11: ret
}

Error: SSA(VReg(vreg = 134, class = Int), Inst(6))
CLIF for error:
function u1:0() fast {
block0:
    v0 = f64const 0.0
    v1 = fcmp uno v0, v0  ; v0 = 0.0, v0 = 0.0
    brz v1, block1
    jump block1

block1:
    return
}

thread 'main' panicked at 'register allocation: SSA(VReg(vreg = 134, class = Int), Inst(6))', cranelift/codegen/src/machinst/compile.rs:67:14

Wasmtime GitHub notifications bot (Dec 30 2022 at 17:56):

afonso360 opened issue #5500:

:wave: Hey,

`.clif` Test Case

test compile
target riscv64

function u1:0() {
block0:
    v0 = f64const 0.0
    v1 = fcmp eq v0, v0
    brz v1, block1
    jump block1

block1:
    return
}

Steps to Reproduce

cargo run -- compile -D --target riscv64 ./the-above.clif

Expected Results

The file to compile

Actual Results

ERROR cranelift_codegen::machinst::compile > Register allocation error for vcode
VCode {
  Entry block: 0
Block 0:
    (original IR block: block0)
    (successor: Block 1)
    (successor: Block 2)
    (instruction range: 0 .. 7)
  Inst 0: li v131,0
  Inst 1: fmv.d.x v130,v131
  Inst 2: li v133,0
  Inst 3: fmv.d.x v132,v133
  Inst 4: feq.d v134,v130,v132
  Inst 5: beq v134,zero,taken(label1),not_taken(0)
  Inst 6: j label2
Block 1:
    (successor: Block 3)
    (instruction range: 7 .. 8)
  Inst 7: j label3
Block 2:
    (successor: Block 3)
    (instruction range: 8 .. 9)
  Inst 8: j label3
Block 3:
    (original IR block: block1)
    (instruction range: 9 .. 10)
  Inst 9: ret
}

Error: BB(Block(0))
CLIF for error:
function u1:0() fast {
block0:
    v0 = f64const 0.0
    v1 = fcmp eq v0, v0  ; v0 = 0.0, v0 = 0.0
    brz v1, block1
    jump block1

block1:
    return
}

thread 'main' panicked at 'register allocation: BB(Block(0))', cranelift/codegen/src/machinst/compile.rs:67:14

Versions and Environment

Cranelift version or commit: main
Operating system: Linux
Architecture: riscv64

Extra Info

Changing the fcmp condition to uno instead of eq gets a slightly better error message.

 ERROR cranelift_codegen::machinst::compile > Register allocation error for vcode
VCode {
  Entry block: 0
Block 0:
    (original IR block: block0)
    (successor: Block 1)
    (successor: Block 2)
    (instruction range: 0 .. 9)
  Inst 0: li v131,0
  Inst 1: fmv.d.x v130,v131
  Inst 2: li v133,0
  Inst 3: fmv.d.x v132,v133
  Inst 4: fle.d v134,v132,v130
  Inst 5: bne v134,zero,taken(label1),not_taken(0)
  Inst 6: flt.d v134,v130,v132
  Inst 7: bne v134,zero,taken(label1),not_taken(0)
  Inst 8: j label2
Block 1:
    (successor: Block 3)
    (instruction range: 9 .. 10)
  Inst 9: j label3
Block 2:
    (successor: Block 3)
    (instruction range: 10 .. 11)
  Inst 10: j label3
Block 3:
    (original IR block: block1)
    (instruction range: 11 .. 12)
  Inst 11: ret
}

Error: SSA(VReg(vreg = 134, class = Int), Inst(6))
CLIF for error:
function u1:0() fast {
block0:
    v0 = f64const 0.0
    v1 = fcmp uno v0, v0  ; v0 = 0.0, v0 = 0.0
    brz v1, block1
    jump block1

block1:
    return
}

thread 'main' panicked at 'register allocation: SSA(VReg(vreg = 134, class = Int), Inst(6))', cranelift/codegen/src/machinst/compile.rs:67:14

Wasmtime GitHub notifications bot (Jan 03 2023 at 19:08):

elliottt commented on issue #5500:

The problem is the beq instruction (5) before the j instruction (6). This came up in a few other places when I did the initial work to enable the SSA checker, so I'll open a PR to handle this one as well.

Wasmtime GitHub notifications bot (Jan 04 2023 at 19:52):

elliottt closed issue #5500:

:wave: Hey,

`.clif` Test Case

test compile
target riscv64

function u1:0() {
block0:
    v0 = f64const 0.0
    v1 = fcmp eq v0, v0
    brz v1, block1
    jump block1

block1:
    return
}

Steps to Reproduce

cargo run -- compile -D --target riscv64 ./the-above.clif

Expected Results

The file to compile

Actual Results

ERROR cranelift_codegen::machinst::compile > Register allocation error for vcode
VCode {
  Entry block: 0
Block 0:
    (original IR block: block0)
    (successor: Block 1)
    (successor: Block 2)
    (instruction range: 0 .. 7)
  Inst 0: li v131,0
  Inst 1: fmv.d.x v130,v131
  Inst 2: li v133,0
  Inst 3: fmv.d.x v132,v133
  Inst 4: feq.d v134,v130,v132
  Inst 5: beq v134,zero,taken(label1),not_taken(0)
  Inst 6: j label2
Block 1:
    (successor: Block 3)
    (instruction range: 7 .. 8)
  Inst 7: j label3
Block 2:
    (successor: Block 3)
    (instruction range: 8 .. 9)
  Inst 8: j label3
Block 3:
    (original IR block: block1)
    (instruction range: 9 .. 10)
  Inst 9: ret
}

Error: BB(Block(0))
CLIF for error:
function u1:0() fast {
block0:
    v0 = f64const 0.0
    v1 = fcmp eq v0, v0  ; v0 = 0.0, v0 = 0.0
    brz v1, block1
    jump block1

block1:
    return
}

thread 'main' panicked at 'register allocation: BB(Block(0))', cranelift/codegen/src/machinst/compile.rs:67:14

Versions and Environment

Cranelift version or commit: main
Operating system: Linux
Architecture: riscv64

Extra Info

Changing the fcmp condition to uno instead of eq gets a slightly better error message.

 ERROR cranelift_codegen::machinst::compile > Register allocation error for vcode
VCode {
  Entry block: 0
Block 0:
    (original IR block: block0)
    (successor: Block 1)
    (successor: Block 2)
    (instruction range: 0 .. 9)
  Inst 0: li v131,0
  Inst 1: fmv.d.x v130,v131
  Inst 2: li v133,0
  Inst 3: fmv.d.x v132,v133
  Inst 4: fle.d v134,v132,v130
  Inst 5: bne v134,zero,taken(label1),not_taken(0)
  Inst 6: flt.d v134,v130,v132
  Inst 7: bne v134,zero,taken(label1),not_taken(0)
  Inst 8: j label2
Block 1:
    (successor: Block 3)
    (instruction range: 9 .. 10)
  Inst 9: j label3
Block 2:
    (successor: Block 3)
    (instruction range: 10 .. 11)
  Inst 10: j label3
Block 3:
    (original IR block: block1)
    (instruction range: 11 .. 12)
  Inst 11: ret
}

Error: SSA(VReg(vreg = 134, class = Int), Inst(6))
CLIF for error:
function u1:0() fast {
block0:
    v0 = f64const 0.0
    v1 = fcmp uno v0, v0  ; v0 = 0.0, v0 = 0.0
    brz v1, block1
    jump block1

block1:
    return
}

thread 'main' panicked at 'register allocation: SSA(VReg(vreg = 134, class = Int), Inst(6))', cranelift/codegen/src/machinst/compile.rs:67:14

Last updated: Oct 23 2024 at 20:03 UTC

Stream: git-wasmtime

Topic: wasmtime / issue #5500 Cranelift: Register allocation err...

Wasmtime GitHub notifications bot (Dec 30 2022 at 17:56):

.clif Test Case

Steps to Reproduce

Expected Results

Actual Results

Versions and Environment

Extra Info

Wasmtime GitHub notifications bot (Dec 30 2022 at 17:56):

.clif Test Case

Steps to Reproduce

Expected Results

Actual Results

Versions and Environment

Extra Info

Wasmtime GitHub notifications bot (Dec 30 2022 at 17:56):

.clif Test Case

Steps to Reproduce

Expected Results

Actual Results

Versions and Environment

Extra Info

Wasmtime GitHub notifications bot (Jan 03 2023 at 19:08):

Wasmtime GitHub notifications bot (Jan 04 2023 at 19:52):

.clif Test Case

Steps to Reproduce

Expected Results

Actual Results

Versions and Environment

Extra Info

`.clif` Test Case

`.clif` Test Case

`.clif` Test Case

`.clif` Test Case