Stream: git-wasmtime

Topic: wasmtime / issue #5498 Cranelift: Illegal instruction on ...


view this post on Zulip Wasmtime GitHub notifications bot (Dec 29 2022 at 23:52):

afonso360 opened issue #5498:

:wave: Hey,

I can't seem to pin down which instruction exactly is causing the issue here, removing any of the ones in the test below make it pass.

.clif Test Case

test interpret
test run
target riscv64

function %a(i16, i8) -> i16 {
block0(v0: i16, v1: i8):
    v2 = ishl v0, v1
    v3 = iconst.i16 0
    v4 = iconst.i16 1
    v5 = icmp eq v2, v3  ; v3 = 0
    v6 = select v5, v4, v2  ; v4 = 1
    v7 = udiv v2, v6
    return v7
}

; run: %a(514, -1) == 0

Steps to Reproduce

Expected Results

The test to pass.

Actual Results

Illegal instruction

Versions and Environment

Cranelift version or commit: main
Operating system: Linux
Architecture: riscv64

Extra Info

Disassembly:

Disassembly of 64 bytes:
   0:   13 f8 f5 00             andi    a6, a1, 0xf
   4:   3b 1e 05 01             sllw    t3, a0, a6
   8:   93 07 00 00             mv      a5, zero
   c:   93 08 10 00             addi    a7, zero, 1
  10:   63 06 fe 00             beq     t3, a5, 0xc
  14:   93 6e 0e 00             ori     t4, t3, 0
  18:   6f 00 80 00             j       8
  1c:   93 ee 08 00             ori     t4, a7, 0
  20:   93 97 0e 03             slli    a5, t4, 0x30
  24:   93 d7 07 03             srli    a5, a5, 0x30
  28:   63 14 f0 00             bne     zero, a5, 8
  2c:   00 00 00 00             .byte   0x00, 0x00, 0x00, 0x00
  30:   13 1e 0e 03             slli    t3, t3, 0x30
  34:   13 5e 0e 03             srli    t3, t3, 0x30
  38:   3b 55 fe 02             divuw   a0, t3, a5
  3c:   67 80 00 00             ret

view this post on Zulip Wasmtime GitHub notifications bot (Dec 29 2022 at 23:52):

afonso360 labeled issue #5498:

:wave: Hey,

I can't seem to pin down which instruction exactly is causing the issue here, removing any of the ones in the test below make it pass.

.clif Test Case

test interpret
test run
target riscv64

function %a(i16, i8) -> i16 {
block0(v0: i16, v1: i8):
    v2 = ishl v0, v1
    v3 = iconst.i16 0
    v4 = iconst.i16 1
    v5 = icmp eq v2, v3  ; v3 = 0
    v6 = select v5, v4, v2  ; v4 = 1
    v7 = udiv v2, v6
    return v7
}

; run: %a(514, -1) == 0

Steps to Reproduce

Expected Results

The test to pass.

Actual Results

Illegal instruction

Versions and Environment

Cranelift version or commit: main
Operating system: Linux
Architecture: riscv64

Extra Info

Disassembly:

Disassembly of 64 bytes:
   0:   13 f8 f5 00             andi    a6, a1, 0xf
   4:   3b 1e 05 01             sllw    t3, a0, a6
   8:   93 07 00 00             mv      a5, zero
   c:   93 08 10 00             addi    a7, zero, 1
  10:   63 06 fe 00             beq     t3, a5, 0xc
  14:   93 6e 0e 00             ori     t4, t3, 0
  18:   6f 00 80 00             j       8
  1c:   93 ee 08 00             ori     t4, a7, 0
  20:   93 97 0e 03             slli    a5, t4, 0x30
  24:   93 d7 07 03             srli    a5, a5, 0x30
  28:   63 14 f0 00             bne     zero, a5, 8
  2c:   00 00 00 00             .byte   0x00, 0x00, 0x00, 0x00
  30:   13 1e 0e 03             slli    t3, t3, 0x30
  34:   13 5e 0e 03             srli    t3, t3, 0x30
  38:   3b 55 fe 02             divuw   a0, t3, a5
  3c:   67 80 00 00             ret

view this post on Zulip Wasmtime GitHub notifications bot (Dec 29 2022 at 23:52):

afonso360 labeled issue #5498:

:wave: Hey,

I can't seem to pin down which instruction exactly is causing the issue here, removing any of the ones in the test below make it pass.

.clif Test Case

test interpret
test run
target riscv64

function %a(i16, i8) -> i16 {
block0(v0: i16, v1: i8):
    v2 = ishl v0, v1
    v3 = iconst.i16 0
    v4 = iconst.i16 1
    v5 = icmp eq v2, v3  ; v3 = 0
    v6 = select v5, v4, v2  ; v4 = 1
    v7 = udiv v2, v6
    return v7
}

; run: %a(514, -1) == 0

Steps to Reproduce

Expected Results

The test to pass.

Actual Results

Illegal instruction

Versions and Environment

Cranelift version or commit: main
Operating system: Linux
Architecture: riscv64

Extra Info

Disassembly:

Disassembly of 64 bytes:
   0:   13 f8 f5 00             andi    a6, a1, 0xf
   4:   3b 1e 05 01             sllw    t3, a0, a6
   8:   93 07 00 00             mv      a5, zero
   c:   93 08 10 00             addi    a7, zero, 1
  10:   63 06 fe 00             beq     t3, a5, 0xc
  14:   93 6e 0e 00             ori     t4, t3, 0
  18:   6f 00 80 00             j       8
  1c:   93 ee 08 00             ori     t4, a7, 0
  20:   93 97 0e 03             slli    a5, t4, 0x30
  24:   93 d7 07 03             srli    a5, a5, 0x30
  28:   63 14 f0 00             bne     zero, a5, 8
  2c:   00 00 00 00             .byte   0x00, 0x00, 0x00, 0x00
  30:   13 1e 0e 03             slli    t3, t3, 0x30
  34:   13 5e 0e 03             srli    t3, t3, 0x30
  38:   3b 55 fe 02             divuw   a0, t3, a5
  3c:   67 80 00 00             ret

view this post on Zulip Wasmtime GitHub notifications bot (Jan 03 2023 at 19:59):

elliottt closed issue #5498:

:wave: Hey,

I can't seem to pin down which instruction exactly is causing the issue here, removing any of the ones in the test below make it pass.

.clif Test Case

test interpret
test run
target riscv64

function %a(i16, i8) -> i16 {
block0(v0: i16, v1: i8):
    v2 = ishl v0, v1
    v3 = iconst.i16 0
    v4 = iconst.i16 1
    v5 = icmp eq v2, v3  ; v3 = 0
    v6 = select v5, v4, v2  ; v4 = 1
    v7 = udiv v2, v6
    return v7
}

; run: %a(514, -1) == 0

Steps to Reproduce

Expected Results

The test to pass.

Actual Results

Illegal instruction

Versions and Environment

Cranelift version or commit: main
Operating system: Linux
Architecture: riscv64

Extra Info

Disassembly:

Disassembly of 64 bytes:
   0:   13 f8 f5 00             andi    a6, a1, 0xf
   4:   3b 1e 05 01             sllw    t3, a0, a6
   8:   93 07 00 00             mv      a5, zero
   c:   93 08 10 00             addi    a7, zero, 1
  10:   63 06 fe 00             beq     t3, a5, 0xc
  14:   93 6e 0e 00             ori     t4, t3, 0
  18:   6f 00 80 00             j       8
  1c:   93 ee 08 00             ori     t4, a7, 0
  20:   93 97 0e 03             slli    a5, t4, 0x30
  24:   93 d7 07 03             srli    a5, a5, 0x30
  28:   63 14 f0 00             bne     zero, a5, 8
  2c:   00 00 00 00             .byte   0x00, 0x00, 0x00, 0x00
  30:   13 1e 0e 03             slli    t3, t3, 0x30
  34:   13 5e 0e 03             srli    t3, t3, 0x30
  38:   3b 55 fe 02             divuw   a0, t3, a5
  3c:   67 80 00 00             ret

Last updated: Dec 23 2024 at 12:05 UTC