Stream: git-wasmtime

Topic: wasmtime / issue #5008 Cranelift: Support tls_value on ri...


view this post on Zulip Wasmtime GitHub notifications bot (Oct 04 2022 at 18:33):

bjorn3 opened issue #5008:

Feature

Support the tls_value instruction on riscv64

Benefit

Necessary for cg_clif to implement thread local storage.

Implementation

https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#global-dynamic shows the instruction sequence with all relocation necessary for performing a tls access with the global dynamic tls model (the most general model). __tls_get_addr here is just a regular function following the riscv C abi. See https://github.com/bytecodealliance/wasmtime/blob/2986f6b0fffd576a2ba88a1fc6cb2db959a1f9e8/cranelift/codegen/src/isa/x64/inst/emit.rs#L3096-L3123 as an example implementation for x86_64 (different instruction sequence, but same principle)

Alternatives

None

cc @yuyang-ok

view this post on Zulip Wasmtime GitHub notifications bot (Jan 06 2023 at 18:37):

elliottt labeled issue #5008:

Feature

Support the tls_value instruction on riscv64

Benefit

Necessary for cg_clif to implement thread local storage.

Implementation

https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#global-dynamic shows the instruction sequence with all relocation necessary for performing a tls access with the global dynamic tls model (the most general model). __tls_get_addr here is just a regular function following the riscv C abi. See https://github.com/bytecodealliance/wasmtime/blob/2986f6b0fffd576a2ba88a1fc6cb2db959a1f9e8/cranelift/codegen/src/isa/x64/inst/emit.rs#L3096-L3123 as an example implementation for x86_64 (different instruction sequence, but same principle)

Alternatives

None

cc @yuyang-ok

view this post on Zulip Wasmtime GitHub notifications bot (Oct 08 2023 at 13:54):

afonso360 commented on issue #5008:

This has been implemented as part of #7003

view this post on Zulip Wasmtime GitHub notifications bot (Oct 08 2023 at 13:54):

afonso360 closed issue #5008:

Feature

Support the tls_value instruction on riscv64

Benefit

Necessary for cg_clif to implement thread local storage.

Implementation

https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#global-dynamic shows the instruction sequence with all relocation necessary for performing a tls access with the global dynamic tls model (the most general model). __tls_get_addr here is just a regular function following the riscv C abi. See https://github.com/bytecodealliance/wasmtime/blob/2986f6b0fffd576a2ba88a1fc6cb2db959a1f9e8/cranelift/codegen/src/isa/x64/inst/emit.rs#L3096-L3123 as an example implementation for x86_64 (different instruction sequence, but same principle)

Alternatives

None

cc @yuyang-ok


Last updated: Dec 23 2024 at 12:05 UTC