alexcrichton labeled issue #4875:
https://oss-fuzz.com/testcase-detail/5189810368675840 - https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=51027
<details>
<summary>Test case input</summary></details>
<details>
<summary>cargo +nightly fuzz fmt
output</summary><!-- If you can, please paste the output of
cargo +nightly fuzz fmt <target> <input>
in the code-block below. This will help reviewers more quickly triage this report. -->;; Fuzzgen test case test interpret test run set enable_llvm_abi_extensions target aarch64 target s390x target x86_64 function u1:0(i32, i64 uext, f32 sext, f64 uext, i128, b1 sext, i8 sext, i128, i16, i16 uext, i16 uext, i16 uext) -> i16, i16 uext, i64, b1, f32 uext, f32, i8 sext, f32, f32 uext, f32 uext, f32 uext system_v { ss0 = explicit_slot 65 ss1 = explicit_slot 65 ss2 = explicit_slot 65 ss3 = explicit_slot 65 ss4 = explicit_slot 65 jt0 = jump_table [] jt1 = jump_table [] jt2 = jump_table [] jt3 = jump_table [block4, block4, block4, block3, block3, block3, block9, block3, block3, block14, block4, block4] jt4 = jump_table [block4, block4, block4, block18, block18, block18, block9, block18, block18, block14, block4, block4] jt5 = jump_table [block4, block4, block4, block18, block18, block18, block25, block18, block18, block14, block4, block4] jt6 = jump_table [block4, block4, block4, block18, block18, block18, block25, block18, block18, block26, block4, block4] block0(v0: i32, v1: i64, v2: f32, v3: f64, v4: i128, v5: b1, v6: i8, v7: i128, v8: i16, v9: i16, v10: i16, v11: i16): v95 -> v0 v145 -> v0 v97 -> v1 v141 -> v1 v337 -> v2 v107 -> v3 v127 -> v3 v136 -> v4 v105 -> v6 v142 -> v6 v92 -> v7 v137 -> v7 v133 -> v8 v94 -> v9 v134 -> v9 v103 -> v10 v150 -> v10 v99 -> v11 v284 -> v11 v59 = f32const 0x1.820000p3 v344 -> v59 v60 = iconst.i8 31 v61 = iconst.i8 65 v153 -> v61 v62 = iconst.i8 65 v139 -> v62 v63 = iconst.i128 0 v64 = iconst.i64 0 v65 = iconst.i32 0 v66 = iconst.i16 0 v67 = iconst.i8 0 stack_store v63, ss0 ; v63 = 0 stack_store v63, ss0+16 ; v63 = 0 stack_store v63, ss0+32 ; v63 = 0 stack_store v63, ss0+48 ; v63 = 0 stack_store v67, ss0+64 ; v67 = 0 stack_store v63, ss1 ; v63 = 0 stack_store v63, ss1+16 ; v63 = 0 stack_store v63, ss1+32 ; v63 = 0 stack_store v63, ss1+48 ; v63 = 0 stack_store v67, ss1+64 ; v67 = 0 stack_store v63, ss2 ; v63 = 0 stack_store v63, ss2+16 ; v63 = 0 stack_store v63, ss2+32 ; v63 = 0 stack_store v63, ss2+48 ; v63 = 0 stack_store v67, ss2+64 ; v67 = 0 stack_store v63, ss3 ; v63 = 0 stack_store v63, ss3+16 ; v63 = 0 stack_store v63, ss3+32 ; v63 = 0 stack_store v63, ss3+48 ; v63 = 0 stack_store v67, ss3+64 ; v67 = 0 stack_store v63, ss4 ; v63 = 0 stack_store v63, ss4+16 ; v63 = 0 stack_store v63, ss4+32 ; v63 = 0 stack_store v63, ss4+48 ; v63 = 0 stack_store v67, ss4+64 ; v67 = 0 v68 = icmp_imm uge v60, 196 ; v60 = 31 brnz v68, block17 jump block5 block17: v69 = iadd_imm.i8 v60, -196 ; v60 = 31 v70 = uextend.i32 v69 br_table v70, block5, jt6 block1(v12: f32, v13: f32, v14: f32, v15: f32, v16: f32, v17: f32, v18: f32, v19: f32, v20: f32, v21: f32, v22: f32, v23: f32, v24: f32, v25: f32, v26: f32, v27: f32): v73 = sshr.i32 v71, v72 ; v71 = 0, v72 = 0 br_icmp ule v73, v73, block3(v77, v90, v75, v375, v26, v27, v74, v73, v82, v425, v88, v84, v72, v85, v78) ; v375 = false, v74 = 0, v425 = 0, v84 = 0, v72 = 0, v78 = 0 jump block14(v75, v74, v73, v82, v425, v88, v84, v72, v85, v78, v77, v90, v26, v27) ; v74 = 0, v425 = 0, v84 = 0, v72 = 0, v78 = 0 block2(v28: f32, v29: i16, v30: f32, v31: i64, v32: i64, v33: i64, v34: i64, v35: i64, v36: i64, v37: i64, v38: i64, v39: i64, v40: i64, v41: i64, v42: i64, v43: i64): v425 = iconst.i8 0 v424 -> v425 v375 = bconst.b1 false v374 -> v375 v282 = iconst.i128 0 v273 -> v282 v72 -> v273 v281 = iconst.i32 0 v272 -> v281 v71 -> v272 v280 = iconst.i16 0 v89 -> v280 v279 = f64const 0.0 v86 -> v279 v278 = iconst.i8 0 v84 -> v278 v277 = iconst.i8 0 v79 -> v277 v276 = iconst.i16 0 v78 -> v276 v275 = iconst.i8 0 v76 -> v275 v274 = iconst.i128 0 v74 -> v274 v75 = ishl v43, v74 ; v74 = 0 nop v77 = iadd v76, v76 ; v76 = 0, v76 = 0 nop v80 = ishl v78, v79 ; v78 = 0, v79 = 0 nop nop v81 = fneg v30 v82 = udiv v29, v78 ; v78 = 0 v83 = fcopysign v28, v28 nop v85 = sshr v84, v74 ; v84 = 0, v74 = 0 v458 = fma v86, v86, v86 ; v86 = 0.0, v86 = 0.0, v86 = 0.0 v459 = fcmp ne v458, v458 v460 = f64const +NaN v87 = select v459, v460, v458 ; v460 = +NaN v88 = udiv v78, v78 ; v78 = 0, v78 = 0 nop v90 = udiv v82, v89 ; v89 = 0 br_icmp ugt v88, v88, block14(v75, v74, v272, v82, v424, v88, v84, v273, v85, v78, v77, v90, v83, v28) ; v74 = 0, v272 = 0, v424 = 0, v84 = 0, v273 = 0, v78 = 0 jump block1(v83, v28, v28, v28, v28, v83, v83, v28, v83, v28, v28, v83, v83, v83, v28, v83) block3(v91: i8, v369: i16, v371: i64, v373: b1, v377: f32, v379: f32, v426: i128, v428: i32, v430: i16, v432: i8, v434: i16, v436: i8, v437: i128, v439: i8, v441: i16): v331 -> v91 v336 -> v369 v265 -> v371 v343 -> v377 v350 -> v379 v266 -> v426 v270 -> v428 v290 -> v430 v295 -> v432 v300 -> v434 v309 -> v436 v315 -> v437 v320 -> v439 v326 -> v441 brnz v91, block9(v369, v371, v373, v377, v91, v379) jump block15 block4: v93 = isub.i128 v92, v92 v96 = sshr.i16 v94, v95 v98 = rotl.i64 v97, v96 v100 = rotl v98, v99 v101 = rotl v100, v96 v102 = rotl v101, v96 v104 = rotl v102, v103 v106 = sshr.i8 v105, v93 v461 = fmul.f64 v107, v107 v462 = fcmp ne v461, v461 v463 = f64const +NaN v108 = select v462, v463, v461 ; v463 = +NaN v464 = fmul v108, v108 v465 = fcmp ne v464, v464 v466 = f64const +NaN v109 = select v465, v466, v464 ; v466 = +NaN v467 = fmul v109, v109 v468 = fcmp ne v467, v467 v469 = f64const +NaN v110 = select v468, v469, v467 ; v469 = +NaN v470 = fmul v110, v110 v471 = fcmp ne v470, v470 v472 = f64const +NaN v111 = select v471, v472, v470 ; v472 = +NaN nop v473 = fmul v111, v111 v474 = fcmp ne v473, v473 v475 = f64const +NaN v112 = select v474, v475, v473 ; v475 = +NaN v476 = fmul v112, v112 v477 = fcmp ne v476, v476 v478 = f64const +NaN v113 = select v477, v478, v476 ; v478 = +NaN v479 = fmul v113, v113 v480 = fcmp ne v479, v479 v481 = f64const +NaN v114 = select v480, v481, v479 ; v481 = +NaN v482 = fmul v114, v114 v483 = fcmp ne v482, v482 v484 = f64const +NaN v115 = select v483, v484, v482 ; v484 = +NaN v485 = fmul v115, v115 v486 = fcmp ne v485, v485 v487 = f64const +NaN v116 = select v486, v487, v485 ; v487 = +NaN v488 = fmul v116, v116 v489 = fcmp ne v488, v488 v490 = f64const +NaN v117 = select v489, v490, v488 ; v490 = +NaN v491 = fmul v117, v117 v492 = fcmp ne v491, v491 v493 = f64const +NaN v118 = select v492, v493, v491 ; v493 = +NaN v494 = fmul v118, v118 v495 = fcmp ne v494, v494 v496 = f64const +NaN v119 = select v495, v496, v494 ; v496 = +NaN v497 = fmul v119, v119 v498 = fcmp ne v497, v497 v499 = f64const +NaN v120 = select v498, v499, v497 ; v499 = +NaN v500 = fmul v120, v120 v501 = fcmp ne v500, v500 v502 = f64const +NaN v121 = select v501, v502, v500 ; v502 = +NaN v503 = fmul v121, v121 v504 = fcmp ne v503, v503 v505 = f64const +NaN v122 = select v504, v505, v503 ; v505 = +NaN v506 = fmul v122, v122 v507 = fcmp ne v506, v506 v508 = f64const +NaN v123 = select v507, v508, v506 ; v508 = +NaN v509 = fmul v123, v123 v510 = fcmp ne v509, v509 v511 = f64const +NaN v124 = select v510, v511, v509 ; v511 = +NaN v512 = fmul v124, v124 v513 = fcmp ne v512, v512 v514 = f64const +NaN v125 = select v513, v514, v512 ; v514 = +NaN v515 = fmul v125, v125 v516 = fcmp ne v515, v515 v517 = f64const +NaN v126 = select v516, v517, v515 ; v517 = +NaN br_table v95, block19, jt2 block5: v518 = fmul.f64 v127, v127 v519 = fcmp ne v518, v518 v520 = f64const +NaN v128 = select v519, v520, v518 ; v520 = +NaN v521 = fmul v128, v128 v522 = fcmp ne v521, v521 v523 = f64const +NaN v129 = select v522, v523, v521 ; v523 = +NaN v524 = fmul v129, v129 v525 = fcmp ne v524, v524 v526 = f64const +NaN v130 = select v525, v526, v524 ; v526 = +NaN v527 = fmul v130, v130 v528 = fcmp ne v527, v527 v529 = f64const +NaN v131 = select v528, v529, v527 ; v529 = +NaN v530 = fmul v131, v131 v531 = fcmp ne v530, v530 v532 = f64const +NaN v132 = select v531, v532, v530 ; v532 = +NaN nop nop nop nop nop nop nop v135 = isub.i16 v133, v134 v138 = iadd.i128 v136, v137 v140 = sextend.i16 v139 ; v139 = 65 v143 = rotr.i64 v141, v142 v144 = iadd.i8 v142, v139 ; v139 = 65 v146 = sextend.i64 v145 v147 = ishl v146, v138 v148 = sshr v138, v147 [message truncated]
alexcrichton labeled issue #4875:
https://oss-fuzz.com/testcase-detail/5189810368675840 - https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=51027
<details>
<summary>Test case input</summary></details>
<details>
<summary>cargo +nightly fuzz fmt
output</summary><!-- If you can, please paste the output of
cargo +nightly fuzz fmt <target> <input>
in the code-block below. This will help reviewers more quickly triage this report. -->;; Fuzzgen test case test interpret test run set enable_llvm_abi_extensions target aarch64 target s390x target x86_64 function u1:0(i32, i64 uext, f32 sext, f64 uext, i128, b1 sext, i8 sext, i128, i16, i16 uext, i16 uext, i16 uext) -> i16, i16 uext, i64, b1, f32 uext, f32, i8 sext, f32, f32 uext, f32 uext, f32 uext system_v { ss0 = explicit_slot 65 ss1 = explicit_slot 65 ss2 = explicit_slot 65 ss3 = explicit_slot 65 ss4 = explicit_slot 65 jt0 = jump_table [] jt1 = jump_table [] jt2 = jump_table [] jt3 = jump_table [block4, block4, block4, block3, block3, block3, block9, block3, block3, block14, block4, block4] jt4 = jump_table [block4, block4, block4, block18, block18, block18, block9, block18, block18, block14, block4, block4] jt5 = jump_table [block4, block4, block4, block18, block18, block18, block25, block18, block18, block14, block4, block4] jt6 = jump_table [block4, block4, block4, block18, block18, block18, block25, block18, block18, block26, block4, block4] block0(v0: i32, v1: i64, v2: f32, v3: f64, v4: i128, v5: b1, v6: i8, v7: i128, v8: i16, v9: i16, v10: i16, v11: i16): v95 -> v0 v145 -> v0 v97 -> v1 v141 -> v1 v337 -> v2 v107 -> v3 v127 -> v3 v136 -> v4 v105 -> v6 v142 -> v6 v92 -> v7 v137 -> v7 v133 -> v8 v94 -> v9 v134 -> v9 v103 -> v10 v150 -> v10 v99 -> v11 v284 -> v11 v59 = f32const 0x1.820000p3 v344 -> v59 v60 = iconst.i8 31 v61 = iconst.i8 65 v153 -> v61 v62 = iconst.i8 65 v139 -> v62 v63 = iconst.i128 0 v64 = iconst.i64 0 v65 = iconst.i32 0 v66 = iconst.i16 0 v67 = iconst.i8 0 stack_store v63, ss0 ; v63 = 0 stack_store v63, ss0+16 ; v63 = 0 stack_store v63, ss0+32 ; v63 = 0 stack_store v63, ss0+48 ; v63 = 0 stack_store v67, ss0+64 ; v67 = 0 stack_store v63, ss1 ; v63 = 0 stack_store v63, ss1+16 ; v63 = 0 stack_store v63, ss1+32 ; v63 = 0 stack_store v63, ss1+48 ; v63 = 0 stack_store v67, ss1+64 ; v67 = 0 stack_store v63, ss2 ; v63 = 0 stack_store v63, ss2+16 ; v63 = 0 stack_store v63, ss2+32 ; v63 = 0 stack_store v63, ss2+48 ; v63 = 0 stack_store v67, ss2+64 ; v67 = 0 stack_store v63, ss3 ; v63 = 0 stack_store v63, ss3+16 ; v63 = 0 stack_store v63, ss3+32 ; v63 = 0 stack_store v63, ss3+48 ; v63 = 0 stack_store v67, ss3+64 ; v67 = 0 stack_store v63, ss4 ; v63 = 0 stack_store v63, ss4+16 ; v63 = 0 stack_store v63, ss4+32 ; v63 = 0 stack_store v63, ss4+48 ; v63 = 0 stack_store v67, ss4+64 ; v67 = 0 v68 = icmp_imm uge v60, 196 ; v60 = 31 brnz v68, block17 jump block5 block17: v69 = iadd_imm.i8 v60, -196 ; v60 = 31 v70 = uextend.i32 v69 br_table v70, block5, jt6 block1(v12: f32, v13: f32, v14: f32, v15: f32, v16: f32, v17: f32, v18: f32, v19: f32, v20: f32, v21: f32, v22: f32, v23: f32, v24: f32, v25: f32, v26: f32, v27: f32): v73 = sshr.i32 v71, v72 ; v71 = 0, v72 = 0 br_icmp ule v73, v73, block3(v77, v90, v75, v375, v26, v27, v74, v73, v82, v425, v88, v84, v72, v85, v78) ; v375 = false, v74 = 0, v425 = 0, v84 = 0, v72 = 0, v78 = 0 jump block14(v75, v74, v73, v82, v425, v88, v84, v72, v85, v78, v77, v90, v26, v27) ; v74 = 0, v425 = 0, v84 = 0, v72 = 0, v78 = 0 block2(v28: f32, v29: i16, v30: f32, v31: i64, v32: i64, v33: i64, v34: i64, v35: i64, v36: i64, v37: i64, v38: i64, v39: i64, v40: i64, v41: i64, v42: i64, v43: i64): v425 = iconst.i8 0 v424 -> v425 v375 = bconst.b1 false v374 -> v375 v282 = iconst.i128 0 v273 -> v282 v72 -> v273 v281 = iconst.i32 0 v272 -> v281 v71 -> v272 v280 = iconst.i16 0 v89 -> v280 v279 = f64const 0.0 v86 -> v279 v278 = iconst.i8 0 v84 -> v278 v277 = iconst.i8 0 v79 -> v277 v276 = iconst.i16 0 v78 -> v276 v275 = iconst.i8 0 v76 -> v275 v274 = iconst.i128 0 v74 -> v274 v75 = ishl v43, v74 ; v74 = 0 nop v77 = iadd v76, v76 ; v76 = 0, v76 = 0 nop v80 = ishl v78, v79 ; v78 = 0, v79 = 0 nop nop v81 = fneg v30 v82 = udiv v29, v78 ; v78 = 0 v83 = fcopysign v28, v28 nop v85 = sshr v84, v74 ; v84 = 0, v74 = 0 v458 = fma v86, v86, v86 ; v86 = 0.0, v86 = 0.0, v86 = 0.0 v459 = fcmp ne v458, v458 v460 = f64const +NaN v87 = select v459, v460, v458 ; v460 = +NaN v88 = udiv v78, v78 ; v78 = 0, v78 = 0 nop v90 = udiv v82, v89 ; v89 = 0 br_icmp ugt v88, v88, block14(v75, v74, v272, v82, v424, v88, v84, v273, v85, v78, v77, v90, v83, v28) ; v74 = 0, v272 = 0, v424 = 0, v84 = 0, v273 = 0, v78 = 0 jump block1(v83, v28, v28, v28, v28, v83, v83, v28, v83, v28, v28, v83, v83, v83, v28, v83) block3(v91: i8, v369: i16, v371: i64, v373: b1, v377: f32, v379: f32, v426: i128, v428: i32, v430: i16, v432: i8, v434: i16, v436: i8, v437: i128, v439: i8, v441: i16): v331 -> v91 v336 -> v369 v265 -> v371 v343 -> v377 v350 -> v379 v266 -> v426 v270 -> v428 v290 -> v430 v295 -> v432 v300 -> v434 v309 -> v436 v315 -> v437 v320 -> v439 v326 -> v441 brnz v91, block9(v369, v371, v373, v377, v91, v379) jump block15 block4: v93 = isub.i128 v92, v92 v96 = sshr.i16 v94, v95 v98 = rotl.i64 v97, v96 v100 = rotl v98, v99 v101 = rotl v100, v96 v102 = rotl v101, v96 v104 = rotl v102, v103 v106 = sshr.i8 v105, v93 v461 = fmul.f64 v107, v107 v462 = fcmp ne v461, v461 v463 = f64const +NaN v108 = select v462, v463, v461 ; v463 = +NaN v464 = fmul v108, v108 v465 = fcmp ne v464, v464 v466 = f64const +NaN v109 = select v465, v466, v464 ; v466 = +NaN v467 = fmul v109, v109 v468 = fcmp ne v467, v467 v469 = f64const +NaN v110 = select v468, v469, v467 ; v469 = +NaN v470 = fmul v110, v110 v471 = fcmp ne v470, v470 v472 = f64const +NaN v111 = select v471, v472, v470 ; v472 = +NaN nop v473 = fmul v111, v111 v474 = fcmp ne v473, v473 v475 = f64const +NaN v112 = select v474, v475, v473 ; v475 = +NaN v476 = fmul v112, v112 v477 = fcmp ne v476, v476 v478 = f64const +NaN v113 = select v477, v478, v476 ; v478 = +NaN v479 = fmul v113, v113 v480 = fcmp ne v479, v479 v481 = f64const +NaN v114 = select v480, v481, v479 ; v481 = +NaN v482 = fmul v114, v114 v483 = fcmp ne v482, v482 v484 = f64const +NaN v115 = select v483, v484, v482 ; v484 = +NaN v485 = fmul v115, v115 v486 = fcmp ne v485, v485 v487 = f64const +NaN v116 = select v486, v487, v485 ; v487 = +NaN v488 = fmul v116, v116 v489 = fcmp ne v488, v488 v490 = f64const +NaN v117 = select v489, v490, v488 ; v490 = +NaN v491 = fmul v117, v117 v492 = fcmp ne v491, v491 v493 = f64const +NaN v118 = select v492, v493, v491 ; v493 = +NaN v494 = fmul v118, v118 v495 = fcmp ne v494, v494 v496 = f64const +NaN v119 = select v495, v496, v494 ; v496 = +NaN v497 = fmul v119, v119 v498 = fcmp ne v497, v497 v499 = f64const +NaN v120 = select v498, v499, v497 ; v499 = +NaN v500 = fmul v120, v120 v501 = fcmp ne v500, v500 v502 = f64const +NaN v121 = select v501, v502, v500 ; v502 = +NaN v503 = fmul v121, v121 v504 = fcmp ne v503, v503 v505 = f64const +NaN v122 = select v504, v505, v503 ; v505 = +NaN v506 = fmul v122, v122 v507 = fcmp ne v506, v506 v508 = f64const +NaN v123 = select v507, v508, v506 ; v508 = +NaN v509 = fmul v123, v123 v510 = fcmp ne v509, v509 v511 = f64const +NaN v124 = select v510, v511, v509 ; v511 = +NaN v512 = fmul v124, v124 v513 = fcmp ne v512, v512 v514 = f64const +NaN v125 = select v513, v514, v512 ; v514 = +NaN v515 = fmul v125, v125 v516 = fcmp ne v515, v515 v517 = f64const +NaN v126 = select v516, v517, v515 ; v517 = +NaN br_table v95, block19, jt2 block5: v518 = fmul.f64 v127, v127 v519 = fcmp ne v518, v518 v520 = f64const +NaN v128 = select v519, v520, v518 ; v520 = +NaN v521 = fmul v128, v128 v522 = fcmp ne v521, v521 v523 = f64const +NaN v129 = select v522, v523, v521 ; v523 = +NaN v524 = fmul v129, v129 v525 = fcmp ne v524, v524 v526 = f64const +NaN v130 = select v525, v526, v524 ; v526 = +NaN v527 = fmul v130, v130 v528 = fcmp ne v527, v527 v529 = f64const +NaN v131 = select v528, v529, v527 ; v529 = +NaN v530 = fmul v131, v131 v531 = fcmp ne v530, v530 v532 = f64const +NaN v132 = select v531, v532, v530 ; v532 = +NaN nop nop nop nop nop nop nop v135 = isub.i16 v133, v134 v138 = iadd.i128 v136, v137 v140 = sextend.i16 v139 ; v139 = 65 v143 = rotr.i64 v141, v142 v144 = iadd.i8 v142, v139 ; v139 = 65 v146 = sextend.i64 v145 v147 = ishl v146, v138 v148 = sshr v138, v147 [message truncated]
alexcrichton opened issue #4875:
https://oss-fuzz.com/testcase-detail/5189810368675840 - https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=51027
<details>
<summary>Test case input</summary></details>
<details>
<summary>cargo +nightly fuzz fmt
output</summary><!-- If you can, please paste the output of
cargo +nightly fuzz fmt <target> <input>
in the code-block below. This will help reviewers more quickly triage this report. -->;; Fuzzgen test case test interpret test run set enable_llvm_abi_extensions target aarch64 target s390x target x86_64 function u1:0(i32, i64 uext, f32 sext, f64 uext, i128, b1 sext, i8 sext, i128, i16, i16 uext, i16 uext, i16 uext) -> i16, i16 uext, i64, b1, f32 uext, f32, i8 sext, f32, f32 uext, f32 uext, f32 uext system_v { ss0 = explicit_slot 65 ss1 = explicit_slot 65 ss2 = explicit_slot 65 ss3 = explicit_slot 65 ss4 = explicit_slot 65 jt0 = jump_table [] jt1 = jump_table [] jt2 = jump_table [] jt3 = jump_table [block4, block4, block4, block3, block3, block3, block9, block3, block3, block14, block4, block4] jt4 = jump_table [block4, block4, block4, block18, block18, block18, block9, block18, block18, block14, block4, block4] jt5 = jump_table [block4, block4, block4, block18, block18, block18, block25, block18, block18, block14, block4, block4] jt6 = jump_table [block4, block4, block4, block18, block18, block18, block25, block18, block18, block26, block4, block4] block0(v0: i32, v1: i64, v2: f32, v3: f64, v4: i128, v5: b1, v6: i8, v7: i128, v8: i16, v9: i16, v10: i16, v11: i16): v95 -> v0 v145 -> v0 v97 -> v1 v141 -> v1 v337 -> v2 v107 -> v3 v127 -> v3 v136 -> v4 v105 -> v6 v142 -> v6 v92 -> v7 v137 -> v7 v133 -> v8 v94 -> v9 v134 -> v9 v103 -> v10 v150 -> v10 v99 -> v11 v284 -> v11 v59 = f32const 0x1.820000p3 v344 -> v59 v60 = iconst.i8 31 v61 = iconst.i8 65 v153 -> v61 v62 = iconst.i8 65 v139 -> v62 v63 = iconst.i128 0 v64 = iconst.i64 0 v65 = iconst.i32 0 v66 = iconst.i16 0 v67 = iconst.i8 0 stack_store v63, ss0 ; v63 = 0 stack_store v63, ss0+16 ; v63 = 0 stack_store v63, ss0+32 ; v63 = 0 stack_store v63, ss0+48 ; v63 = 0 stack_store v67, ss0+64 ; v67 = 0 stack_store v63, ss1 ; v63 = 0 stack_store v63, ss1+16 ; v63 = 0 stack_store v63, ss1+32 ; v63 = 0 stack_store v63, ss1+48 ; v63 = 0 stack_store v67, ss1+64 ; v67 = 0 stack_store v63, ss2 ; v63 = 0 stack_store v63, ss2+16 ; v63 = 0 stack_store v63, ss2+32 ; v63 = 0 stack_store v63, ss2+48 ; v63 = 0 stack_store v67, ss2+64 ; v67 = 0 stack_store v63, ss3 ; v63 = 0 stack_store v63, ss3+16 ; v63 = 0 stack_store v63, ss3+32 ; v63 = 0 stack_store v63, ss3+48 ; v63 = 0 stack_store v67, ss3+64 ; v67 = 0 stack_store v63, ss4 ; v63 = 0 stack_store v63, ss4+16 ; v63 = 0 stack_store v63, ss4+32 ; v63 = 0 stack_store v63, ss4+48 ; v63 = 0 stack_store v67, ss4+64 ; v67 = 0 v68 = icmp_imm uge v60, 196 ; v60 = 31 brnz v68, block17 jump block5 block17: v69 = iadd_imm.i8 v60, -196 ; v60 = 31 v70 = uextend.i32 v69 br_table v70, block5, jt6 block1(v12: f32, v13: f32, v14: f32, v15: f32, v16: f32, v17: f32, v18: f32, v19: f32, v20: f32, v21: f32, v22: f32, v23: f32, v24: f32, v25: f32, v26: f32, v27: f32): v73 = sshr.i32 v71, v72 ; v71 = 0, v72 = 0 br_icmp ule v73, v73, block3(v77, v90, v75, v375, v26, v27, v74, v73, v82, v425, v88, v84, v72, v85, v78) ; v375 = false, v74 = 0, v425 = 0, v84 = 0, v72 = 0, v78 = 0 jump block14(v75, v74, v73, v82, v425, v88, v84, v72, v85, v78, v77, v90, v26, v27) ; v74 = 0, v425 = 0, v84 = 0, v72 = 0, v78 = 0 block2(v28: f32, v29: i16, v30: f32, v31: i64, v32: i64, v33: i64, v34: i64, v35: i64, v36: i64, v37: i64, v38: i64, v39: i64, v40: i64, v41: i64, v42: i64, v43: i64): v425 = iconst.i8 0 v424 -> v425 v375 = bconst.b1 false v374 -> v375 v282 = iconst.i128 0 v273 -> v282 v72 -> v273 v281 = iconst.i32 0 v272 -> v281 v71 -> v272 v280 = iconst.i16 0 v89 -> v280 v279 = f64const 0.0 v86 -> v279 v278 = iconst.i8 0 v84 -> v278 v277 = iconst.i8 0 v79 -> v277 v276 = iconst.i16 0 v78 -> v276 v275 = iconst.i8 0 v76 -> v275 v274 = iconst.i128 0 v74 -> v274 v75 = ishl v43, v74 ; v74 = 0 nop v77 = iadd v76, v76 ; v76 = 0, v76 = 0 nop v80 = ishl v78, v79 ; v78 = 0, v79 = 0 nop nop v81 = fneg v30 v82 = udiv v29, v78 ; v78 = 0 v83 = fcopysign v28, v28 nop v85 = sshr v84, v74 ; v84 = 0, v74 = 0 v458 = fma v86, v86, v86 ; v86 = 0.0, v86 = 0.0, v86 = 0.0 v459 = fcmp ne v458, v458 v460 = f64const +NaN v87 = select v459, v460, v458 ; v460 = +NaN v88 = udiv v78, v78 ; v78 = 0, v78 = 0 nop v90 = udiv v82, v89 ; v89 = 0 br_icmp ugt v88, v88, block14(v75, v74, v272, v82, v424, v88, v84, v273, v85, v78, v77, v90, v83, v28) ; v74 = 0, v272 = 0, v424 = 0, v84 = 0, v273 = 0, v78 = 0 jump block1(v83, v28, v28, v28, v28, v83, v83, v28, v83, v28, v28, v83, v83, v83, v28, v83) block3(v91: i8, v369: i16, v371: i64, v373: b1, v377: f32, v379: f32, v426: i128, v428: i32, v430: i16, v432: i8, v434: i16, v436: i8, v437: i128, v439: i8, v441: i16): v331 -> v91 v336 -> v369 v265 -> v371 v343 -> v377 v350 -> v379 v266 -> v426 v270 -> v428 v290 -> v430 v295 -> v432 v300 -> v434 v309 -> v436 v315 -> v437 v320 -> v439 v326 -> v441 brnz v91, block9(v369, v371, v373, v377, v91, v379) jump block15 block4: v93 = isub.i128 v92, v92 v96 = sshr.i16 v94, v95 v98 = rotl.i64 v97, v96 v100 = rotl v98, v99 v101 = rotl v100, v96 v102 = rotl v101, v96 v104 = rotl v102, v103 v106 = sshr.i8 v105, v93 v461 = fmul.f64 v107, v107 v462 = fcmp ne v461, v461 v463 = f64const +NaN v108 = select v462, v463, v461 ; v463 = +NaN v464 = fmul v108, v108 v465 = fcmp ne v464, v464 v466 = f64const +NaN v109 = select v465, v466, v464 ; v466 = +NaN v467 = fmul v109, v109 v468 = fcmp ne v467, v467 v469 = f64const +NaN v110 = select v468, v469, v467 ; v469 = +NaN v470 = fmul v110, v110 v471 = fcmp ne v470, v470 v472 = f64const +NaN v111 = select v471, v472, v470 ; v472 = +NaN nop v473 = fmul v111, v111 v474 = fcmp ne v473, v473 v475 = f64const +NaN v112 = select v474, v475, v473 ; v475 = +NaN v476 = fmul v112, v112 v477 = fcmp ne v476, v476 v478 = f64const +NaN v113 = select v477, v478, v476 ; v478 = +NaN v479 = fmul v113, v113 v480 = fcmp ne v479, v479 v481 = f64const +NaN v114 = select v480, v481, v479 ; v481 = +NaN v482 = fmul v114, v114 v483 = fcmp ne v482, v482 v484 = f64const +NaN v115 = select v483, v484, v482 ; v484 = +NaN v485 = fmul v115, v115 v486 = fcmp ne v485, v485 v487 = f64const +NaN v116 = select v486, v487, v485 ; v487 = +NaN v488 = fmul v116, v116 v489 = fcmp ne v488, v488 v490 = f64const +NaN v117 = select v489, v490, v488 ; v490 = +NaN v491 = fmul v117, v117 v492 = fcmp ne v491, v491 v493 = f64const +NaN v118 = select v492, v493, v491 ; v493 = +NaN v494 = fmul v118, v118 v495 = fcmp ne v494, v494 v496 = f64const +NaN v119 = select v495, v496, v494 ; v496 = +NaN v497 = fmul v119, v119 v498 = fcmp ne v497, v497 v499 = f64const +NaN v120 = select v498, v499, v497 ; v499 = +NaN v500 = fmul v120, v120 v501 = fcmp ne v500, v500 v502 = f64const +NaN v121 = select v501, v502, v500 ; v502 = +NaN v503 = fmul v121, v121 v504 = fcmp ne v503, v503 v505 = f64const +NaN v122 = select v504, v505, v503 ; v505 = +NaN v506 = fmul v122, v122 v507 = fcmp ne v506, v506 v508 = f64const +NaN v123 = select v507, v508, v506 ; v508 = +NaN v509 = fmul v123, v123 v510 = fcmp ne v509, v509 v511 = f64const +NaN v124 = select v510, v511, v509 ; v511 = +NaN v512 = fmul v124, v124 v513 = fcmp ne v512, v512 v514 = f64const +NaN v125 = select v513, v514, v512 ; v514 = +NaN v515 = fmul v125, v125 v516 = fcmp ne v515, v515 v517 = f64const +NaN v126 = select v516, v517, v515 ; v517 = +NaN br_table v95, block19, jt2 block5: v518 = fmul.f64 v127, v127 v519 = fcmp ne v518, v518 v520 = f64const +NaN v128 = select v519, v520, v518 ; v520 = +NaN v521 = fmul v128, v128 v522 = fcmp ne v521, v521 v523 = f64const +NaN v129 = select v522, v523, v521 ; v523 = +NaN v524 = fmul v129, v129 v525 = fcmp ne v524, v524 v526 = f64const +NaN v130 = select v525, v526, v524 ; v526 = +NaN v527 = fmul v130, v130 v528 = fcmp ne v527, v527 v529 = f64const +NaN v131 = select v528, v529, v527 ; v529 = +NaN v530 = fmul v131, v131 v531 = fcmp ne v530, v530 v532 = f64const +NaN v132 = select v531, v532, v530 ; v532 = +NaN nop nop nop nop nop nop nop v135 = isub.i16 v133, v134 v138 = iadd.i128 v136, v137 v140 = sextend.i16 v139 ; v139 = 65 v143 = rotr.i64 v141, v142 v144 = iadd.i8 v142, v139 ; v139 = 65 v146 = sextend.i64 v145 v147 = ishl v146, v138 v148 = sshr v138, v147 [message truncated]
afonso360 commented on issue #4875:
The clif test case printed in this bug report is also not runnable which is interesting:
FAIL .\lmao.clif: failed to parse .\lmao.clif Caused by: 530: type variable required for polymorphic opcode, e.g. 'rotl.i32'; can't infer from v255 which is not yet defined 1 tests Error: 1 failure
I suspect this is a separate issue with the clif printer, since the actual code did run in both the interpreter and the backend
afonso360 edited a comment on issue #4875:
The clif test case printed in this bug report is also not runnable which is interesting:
FAIL .\lmao.clif: failed to parse .\lmao.clif Caused by: 530: type variable required for polymorphic opcode, e.g. 'rotl.i32'; can't infer from v255 which is not yet defined 1 tests Error: 1 failure
I suspect this is a separate issue with the clif printer, since the actual code did run in both the interpreter and the backend.
Relevant lines in
block13
:v257 = rotl v255, v256 ; v256 = 0 v255 -> v257
afonso360 commented on issue #4875:
Minimized this to:
test interpret test run target x86_64 function %a() -> b1 { block0: v0 = iconst.i8 -63 v1 = iconst.i8 65 v2 = icmp.i8 nof v1, v0 return v2 } ; run: %a() == false
afonso360 edited a comment on issue #4875:
Minimized this to:
test interpret test run target x86_64 function %a() -> b1 { block0: v0 = iconst.i8 193 v1 = iconst.i8 65 v2 = icmp.i8 nof v1, v0 return v2 } ; run: %a() == false
afonso360 commented on issue #4875:
Tracked this down to 63c2d1e0c34ff7b4452e50b8fa74218bf9ceb00e, reverting that seems to fix this (although probably not what we want to do here). CC: @elliottt
jameysharp commented on issue #4875:
v257 = rotl v255, v256 ; v256 = 0 v255 -> v257
Although this isn't relevant to the fuzz bug, I'm actually kind of worried about this: the definition of
v257
usesv255
, but that's just an alias forv257
, so this instruction depends on itself.
afonso360 commented on issue #4875:
v257 = rotl v255, v256 ; v256 = 0
v255 -> v257Although this isn't relevant to the fuzz bug, I'm actually kind of worried about this: the definition of v257 uses v255, but that's > just an alias for v257, so this instruction depends on itself.
Yeah that is really weird. I won't be able to properly look into this until the weekend, but here's my thoughts:
I think this is either a bug in the frontend or the inst printer.
We don't directly emit aliases in fuzzgen, we always use variables for all operations and let the frontend figure it out.
I think we run the verifier via the JIT on all inputs (I had a quick look and I don't think we disable it anywhere), so at least the verifier thought this was ok? But once printed its no longer ok, that's what initially made me think this was a inst printer issue.
afonso360 edited a comment on issue #4875:
v257 = rotl v255, v256 ; v256 = 0
v255 -> v257Although this isn't relevant to the fuzz bug, I'm actually kind of worried about this: the definition of v257 uses v255, but that's just an alias for v257, so this instruction depends on itself.
Yeah that is really weird. I won't be able to properly look into this until the weekend, but here's my thoughts:
I think this is either a bug in the frontend or the inst printer.
We don't directly emit aliases in fuzzgen, we always use variables for all operations and let the frontend figure it out.
I think we run the verifier via the JIT on all inputs (I had a quick look and I don't think we disable it anywhere), so at least the verifier thought this was ok? But once printed its no longer ok, that's what initially made me think this was a inst printer issue.
afonso360 edited a comment on issue #4875:
v257 = rotl v255, v256 ; v256 = 0
v255 -> v257Although this isn't relevant to the fuzz bug, I'm actually kind of worried about this: the definition of v257 uses v255, but that's just an alias for v257, so this instruction depends on itself.
Yeah that is really weird. I won't be able to properly look into this until the weekend, but here's my thoughts:
I think this is either a bug in the frontend or the inst printer.
We don't directly emit aliases in fuzzgen, we always use variables for all operations and let the frontend figure it out.
I think we run the verifier via the JIT on all inputs (I had a quick look and I don't think we disable it anywhere, ill have to double check), so at least the verifier thought this was ok? But once printed its no longer ok, that's what initially made me think this was a inst printer issue.
afonso360 edited a comment on issue #4875:
v257 = rotl v255, v256 ; v256 = 0
v255 -> v257Although this isn't relevant to the fuzz bug, I'm actually kind of worried about this: the definition of v257 uses v255, but that's just an alias for v257, so this instruction depends on itself.
Yeah that is really weird. I won't be able to properly look into this until the weekend, but here's my thoughts:
I think this is either a bug in the frontend or the inst printer.
We don't directly emit aliases in fuzzgen, we always use variables for all operations and let the frontend figure it out.
I think we run the verifier via the JIT on all inputs (I had a quick look and I don't see us disable it anywhere, ill have to double check), so at least the verifier thought this was ok? But once printed its no longer ok, that's what initially made me suspect this was a inst printer issue.
jameysharp closed issue #4875:
https://oss-fuzz.com/testcase-detail/5189810368675840 - https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=51027
<details>
<summary>Test case input</summary></details>
<details>
<summary>cargo +nightly fuzz fmt
output</summary><!-- If you can, please paste the output of
cargo +nightly fuzz fmt <target> <input>
in the code-block below. This will help reviewers more quickly triage this report. -->;; Fuzzgen test case test interpret test run set enable_llvm_abi_extensions target aarch64 target s390x target x86_64 function u1:0(i32, i64 uext, f32 sext, f64 uext, i128, b1 sext, i8 sext, i128, i16, i16 uext, i16 uext, i16 uext) -> i16, i16 uext, i64, b1, f32 uext, f32, i8 sext, f32, f32 uext, f32 uext, f32 uext system_v { ss0 = explicit_slot 65 ss1 = explicit_slot 65 ss2 = explicit_slot 65 ss3 = explicit_slot 65 ss4 = explicit_slot 65 jt0 = jump_table [] jt1 = jump_table [] jt2 = jump_table [] jt3 = jump_table [block4, block4, block4, block3, block3, block3, block9, block3, block3, block14, block4, block4] jt4 = jump_table [block4, block4, block4, block18, block18, block18, block9, block18, block18, block14, block4, block4] jt5 = jump_table [block4, block4, block4, block18, block18, block18, block25, block18, block18, block14, block4, block4] jt6 = jump_table [block4, block4, block4, block18, block18, block18, block25, block18, block18, block26, block4, block4] block0(v0: i32, v1: i64, v2: f32, v3: f64, v4: i128, v5: b1, v6: i8, v7: i128, v8: i16, v9: i16, v10: i16, v11: i16): v95 -> v0 v145 -> v0 v97 -> v1 v141 -> v1 v337 -> v2 v107 -> v3 v127 -> v3 v136 -> v4 v105 -> v6 v142 -> v6 v92 -> v7 v137 -> v7 v133 -> v8 v94 -> v9 v134 -> v9 v103 -> v10 v150 -> v10 v99 -> v11 v284 -> v11 v59 = f32const 0x1.820000p3 v344 -> v59 v60 = iconst.i8 31 v61 = iconst.i8 65 v153 -> v61 v62 = iconst.i8 65 v139 -> v62 v63 = iconst.i128 0 v64 = iconst.i64 0 v65 = iconst.i32 0 v66 = iconst.i16 0 v67 = iconst.i8 0 stack_store v63, ss0 ; v63 = 0 stack_store v63, ss0+16 ; v63 = 0 stack_store v63, ss0+32 ; v63 = 0 stack_store v63, ss0+48 ; v63 = 0 stack_store v67, ss0+64 ; v67 = 0 stack_store v63, ss1 ; v63 = 0 stack_store v63, ss1+16 ; v63 = 0 stack_store v63, ss1+32 ; v63 = 0 stack_store v63, ss1+48 ; v63 = 0 stack_store v67, ss1+64 ; v67 = 0 stack_store v63, ss2 ; v63 = 0 stack_store v63, ss2+16 ; v63 = 0 stack_store v63, ss2+32 ; v63 = 0 stack_store v63, ss2+48 ; v63 = 0 stack_store v67, ss2+64 ; v67 = 0 stack_store v63, ss3 ; v63 = 0 stack_store v63, ss3+16 ; v63 = 0 stack_store v63, ss3+32 ; v63 = 0 stack_store v63, ss3+48 ; v63 = 0 stack_store v67, ss3+64 ; v67 = 0 stack_store v63, ss4 ; v63 = 0 stack_store v63, ss4+16 ; v63 = 0 stack_store v63, ss4+32 ; v63 = 0 stack_store v63, ss4+48 ; v63 = 0 stack_store v67, ss4+64 ; v67 = 0 v68 = icmp_imm uge v60, 196 ; v60 = 31 brnz v68, block17 jump block5 block17: v69 = iadd_imm.i8 v60, -196 ; v60 = 31 v70 = uextend.i32 v69 br_table v70, block5, jt6 block1(v12: f32, v13: f32, v14: f32, v15: f32, v16: f32, v17: f32, v18: f32, v19: f32, v20: f32, v21: f32, v22: f32, v23: f32, v24: f32, v25: f32, v26: f32, v27: f32): v73 = sshr.i32 v71, v72 ; v71 = 0, v72 = 0 br_icmp ule v73, v73, block3(v77, v90, v75, v375, v26, v27, v74, v73, v82, v425, v88, v84, v72, v85, v78) ; v375 = false, v74 = 0, v425 = 0, v84 = 0, v72 = 0, v78 = 0 jump block14(v75, v74, v73, v82, v425, v88, v84, v72, v85, v78, v77, v90, v26, v27) ; v74 = 0, v425 = 0, v84 = 0, v72 = 0, v78 = 0 block2(v28: f32, v29: i16, v30: f32, v31: i64, v32: i64, v33: i64, v34: i64, v35: i64, v36: i64, v37: i64, v38: i64, v39: i64, v40: i64, v41: i64, v42: i64, v43: i64): v425 = iconst.i8 0 v424 -> v425 v375 = bconst.b1 false v374 -> v375 v282 = iconst.i128 0 v273 -> v282 v72 -> v273 v281 = iconst.i32 0 v272 -> v281 v71 -> v272 v280 = iconst.i16 0 v89 -> v280 v279 = f64const 0.0 v86 -> v279 v278 = iconst.i8 0 v84 -> v278 v277 = iconst.i8 0 v79 -> v277 v276 = iconst.i16 0 v78 -> v276 v275 = iconst.i8 0 v76 -> v275 v274 = iconst.i128 0 v74 -> v274 v75 = ishl v43, v74 ; v74 = 0 nop v77 = iadd v76, v76 ; v76 = 0, v76 = 0 nop v80 = ishl v78, v79 ; v78 = 0, v79 = 0 nop nop v81 = fneg v30 v82 = udiv v29, v78 ; v78 = 0 v83 = fcopysign v28, v28 nop v85 = sshr v84, v74 ; v84 = 0, v74 = 0 v458 = fma v86, v86, v86 ; v86 = 0.0, v86 = 0.0, v86 = 0.0 v459 = fcmp ne v458, v458 v460 = f64const +NaN v87 = select v459, v460, v458 ; v460 = +NaN v88 = udiv v78, v78 ; v78 = 0, v78 = 0 nop v90 = udiv v82, v89 ; v89 = 0 br_icmp ugt v88, v88, block14(v75, v74, v272, v82, v424, v88, v84, v273, v85, v78, v77, v90, v83, v28) ; v74 = 0, v272 = 0, v424 = 0, v84 = 0, v273 = 0, v78 = 0 jump block1(v83, v28, v28, v28, v28, v83, v83, v28, v83, v28, v28, v83, v83, v83, v28, v83) block3(v91: i8, v369: i16, v371: i64, v373: b1, v377: f32, v379: f32, v426: i128, v428: i32, v430: i16, v432: i8, v434: i16, v436: i8, v437: i128, v439: i8, v441: i16): v331 -> v91 v336 -> v369 v265 -> v371 v343 -> v377 v350 -> v379 v266 -> v426 v270 -> v428 v290 -> v430 v295 -> v432 v300 -> v434 v309 -> v436 v315 -> v437 v320 -> v439 v326 -> v441 brnz v91, block9(v369, v371, v373, v377, v91, v379) jump block15 block4: v93 = isub.i128 v92, v92 v96 = sshr.i16 v94, v95 v98 = rotl.i64 v97, v96 v100 = rotl v98, v99 v101 = rotl v100, v96 v102 = rotl v101, v96 v104 = rotl v102, v103 v106 = sshr.i8 v105, v93 v461 = fmul.f64 v107, v107 v462 = fcmp ne v461, v461 v463 = f64const +NaN v108 = select v462, v463, v461 ; v463 = +NaN v464 = fmul v108, v108 v465 = fcmp ne v464, v464 v466 = f64const +NaN v109 = select v465, v466, v464 ; v466 = +NaN v467 = fmul v109, v109 v468 = fcmp ne v467, v467 v469 = f64const +NaN v110 = select v468, v469, v467 ; v469 = +NaN v470 = fmul v110, v110 v471 = fcmp ne v470, v470 v472 = f64const +NaN v111 = select v471, v472, v470 ; v472 = +NaN nop v473 = fmul v111, v111 v474 = fcmp ne v473, v473 v475 = f64const +NaN v112 = select v474, v475, v473 ; v475 = +NaN v476 = fmul v112, v112 v477 = fcmp ne v476, v476 v478 = f64const +NaN v113 = select v477, v478, v476 ; v478 = +NaN v479 = fmul v113, v113 v480 = fcmp ne v479, v479 v481 = f64const +NaN v114 = select v480, v481, v479 ; v481 = +NaN v482 = fmul v114, v114 v483 = fcmp ne v482, v482 v484 = f64const +NaN v115 = select v483, v484, v482 ; v484 = +NaN v485 = fmul v115, v115 v486 = fcmp ne v485, v485 v487 = f64const +NaN v116 = select v486, v487, v485 ; v487 = +NaN v488 = fmul v116, v116 v489 = fcmp ne v488, v488 v490 = f64const +NaN v117 = select v489, v490, v488 ; v490 = +NaN v491 = fmul v117, v117 v492 = fcmp ne v491, v491 v493 = f64const +NaN v118 = select v492, v493, v491 ; v493 = +NaN v494 = fmul v118, v118 v495 = fcmp ne v494, v494 v496 = f64const +NaN v119 = select v495, v496, v494 ; v496 = +NaN v497 = fmul v119, v119 v498 = fcmp ne v497, v497 v499 = f64const +NaN v120 = select v498, v499, v497 ; v499 = +NaN v500 = fmul v120, v120 v501 = fcmp ne v500, v500 v502 = f64const +NaN v121 = select v501, v502, v500 ; v502 = +NaN v503 = fmul v121, v121 v504 = fcmp ne v503, v503 v505 = f64const +NaN v122 = select v504, v505, v503 ; v505 = +NaN v506 = fmul v122, v122 v507 = fcmp ne v506, v506 v508 = f64const +NaN v123 = select v507, v508, v506 ; v508 = +NaN v509 = fmul v123, v123 v510 = fcmp ne v509, v509 v511 = f64const +NaN v124 = select v510, v511, v509 ; v511 = +NaN v512 = fmul v124, v124 v513 = fcmp ne v512, v512 v514 = f64const +NaN v125 = select v513, v514, v512 ; v514 = +NaN v515 = fmul v125, v125 v516 = fcmp ne v515, v515 v517 = f64const +NaN v126 = select v516, v517, v515 ; v517 = +NaN br_table v95, block19, jt2 block5: v518 = fmul.f64 v127, v127 v519 = fcmp ne v518, v518 v520 = f64const +NaN v128 = select v519, v520, v518 ; v520 = +NaN v521 = fmul v128, v128 v522 = fcmp ne v521, v521 v523 = f64const +NaN v129 = select v522, v523, v521 ; v523 = +NaN v524 = fmul v129, v129 v525 = fcmp ne v524, v524 v526 = f64const +NaN v130 = select v525, v526, v524 ; v526 = +NaN v527 = fmul v130, v130 v528 = fcmp ne v527, v527 v529 = f64const +NaN v131 = select v528, v529, v527 ; v529 = +NaN v530 = fmul v131, v131 v531 = fcmp ne v530, v530 v532 = f64const +NaN v132 = select v531, v532, v530 ; v532 = +NaN nop nop nop nop nop nop nop v135 = isub.i16 v133, v134 v138 = iadd.i128 v136, v137 v140 = sextend.i16 v139 ; v139 = 65 v143 = rotr.i64 v141, v142 v144 = iadd.i8 v142, v139 ; v139 = 65 v146 = sextend.i64 v145 v147 = ishl v146, v138 v148 = sshr v138, v147 v1 [message truncated]
Last updated: Dec 23 2024 at 12:05 UTC