Stream: git-wasmtime

Topic: wasmtime / issue #4803 [cranelift][x64][arm] Folding fneg...

Wasmtime GitHub notifications bot (Aug 29 2022 at 12:37):

MaxGraey edited issue #4803:

fneg(fabs(x)) could be possible after copysign(x, -C) -> fneg(fabs(x)) peephole optimization on LLVM / Binaryen, so I guess it's make sense to simplify it further on cranelift during lowering stage.

x64:

orsd xmm0, #0x8000000000000000

armv7:

orr r1, r1, #-2147483648

ppc:

fnabs 1,1
blr

s390x:

lndbr   %f0,%f0
br      %r14

the rest is preserving fneg + fabs

Wasmtime GitHub notifications bot (Aug 30 2022 at 00:03):

jameysharp commented on issue #4803:

I think this looks like a good candidate to work on after @cfallin's mid-end optimizer work lands.

Wasmtime GitHub notifications bot (Aug 30 2022 at 04:46):

MaxGraey edited issue #4803:

fneg(fabs(x)) could be possible after copysign(x, -C) -> fneg(fabs(x)) peephole optimization on LLVM / Binaryen, so I guess it's make sense to simplify it further on cranelift during lowering stage.

x64:

orsd xmm0, #0x8000000000000000

armv7:

orr r1, r1, #-2147483648

ppc:

fnabs 1,1

s390x:

lndbr   %f0,%f0

the rest is preserving fneg + fabs

Wasmtime GitHub notifications bot (Aug 30 2022 at 14:34):

akirilov-arm commented on issue #4803:

While Cranelift does not support the 32-bit Arm architecture, I would like to mention that the armv7 lowering is non-sensical because it operates on general-purpose registers (instead of floating-point ones), unless the code is meant to comply with one of the soft float ABIs and the operations are the first ones in the procedure, so that the input value has not been moved into a floating-point register yet.

Wasmtime GitHub notifications bot (Aug 30 2022 at 19:51):

MaxGraey edited issue #4803:

fneg(fabs(x)) could be possible after copysign(x, -C) -> fneg(fabs(x)) peephole optimization on LLVM / Binaryen, so I guess it's make sense to simplify it further on cranelift during lowering stage.

x64:

orsd xmm0, #0x8000000000000000

ppc:

fnabs 1,1

s390x:

lndbr   %f0,%f0

the rest is preserving fneg + fabs

Wasmtime GitHub notifications bot (Aug 30 2022 at 19:53):

MaxGraey commented on issue #4803:

@akirilov-arm Thanks for the clarification. I removed the mention of armv7

Wasmtime GitHub notifications bot (Sep 02 2022 at 15:39):

akirilov-arm labeled issue #4803:

fneg(fabs(x)) could be possible after copysign(x, -C) -> fneg(fabs(x)) peephole optimization on LLVM / Binaryen, so I guess it's make sense to simplify it further on cranelift during lowering stage.

x64:

orsd xmm0, #0x8000000000000000

ppc:

fnabs 1,1

s390x:

lndbr   %f0,%f0

the rest is preserving fneg + fabs

Wasmtime GitHub notifications bot (Sep 02 2022 at 15:39):

akirilov-arm labeled issue #4803:

fneg(fabs(x)) could be possible after copysign(x, -C) -> fneg(fabs(x)) peephole optimization on LLVM / Binaryen, so I guess it's make sense to simplify it further on cranelift during lowering stage.

x64:

orsd xmm0, #0x8000000000000000

ppc:

fnabs 1,1

s390x:

lndbr   %f0,%f0

the rest is preserving fneg + fabs

Wasmtime GitHub notifications bot (Sep 02 2022 at 15:39):

akirilov-arm labeled issue #4803:

fneg(fabs(x)) could be possible after copysign(x, -C) -> fneg(fabs(x)) peephole optimization on LLVM / Binaryen, so I guess it's make sense to simplify it further on cranelift during lowering stage.

x64:

orsd xmm0, #0x8000000000000000

ppc:

fnabs 1,1

s390x:

lndbr   %f0,%f0

the rest is preserving fneg + fabs

Wasmtime GitHub notifications bot (Sep 02 2022 at 15:39):

akirilov-arm labeled issue #4803:

fneg(fabs(x)) could be possible after copysign(x, -C) -> fneg(fabs(x)) peephole optimization on LLVM / Binaryen, so I guess it's make sense to simplify it further on cranelift during lowering stage.

x64:

orsd xmm0, #0x8000000000000000

ppc:

fnabs 1,1

s390x:

lndbr   %f0,%f0

the rest is preserving fneg + fabs

Wasmtime GitHub notifications bot (Sep 02 2022 at 15:39):

akirilov-arm labeled issue #4803:

fneg(fabs(x)) could be possible after copysign(x, -C) -> fneg(fabs(x)) peephole optimization on LLVM / Binaryen, so I guess it's make sense to simplify it further on cranelift during lowering stage.

x64:

orsd xmm0, #0x8000000000000000

ppc:

fnabs 1,1

s390x:

lndbr   %f0,%f0

the rest is preserving fneg + fabs

Last updated: Dec 23 2024 at 12:05 UTC