wasmtime / issue #4110 cannot get the accurate type just ... · git-wasmtime

Stream: git-wasmtime

Topic: wasmtime / issue #4110 cannot get the accurate type just ...

Wasmtime GitHub notifications bot (May 08 2022 at 10:30):

yuyang-ok edited issue #4110:

running 1 test
TRACE - ABI: func signature Signature { params: [AbiParam { value_type: types::F32, purpose: Normal, extension: None, legalized_to_pointer: false }, AbiParam { value_type: types::F32, purpose: Normal, extension: None, legalized_to_pointer: false }], returns: [AbiParam { value_type: types::F32, purpose: Normal, extension: None, legalized_to_pointer: false }], call_conv: SystemV }
TRACE - ABISig: sig Signature { params: [AbiParam { value_type: types::F32, purpose: Normal, extension: None, legalized_to_pointer: false }, AbiParam { value_type: types::F32, purpose: Normal, extension: None, legalized_to_pointer: false }], returns: [AbiParam { value_type: types::F32, purpose: Normal, extension: None, legalized_to_pointer: false }], call_conv: SystemV } => args = [Slots { slots: [Reg { reg: p10f, ty: types::F32, extension: None }], purpose: Normal }, Slots { slots: [Reg { reg: p11f, ty: types::F32, extension: None }], purpose: Normal }] rets = [Slots { slots: [Reg { reg: p10f, ty: types::F32, extension: None }], purpose: Normal }] arg stack = 0 ret stack = 0 stack_ret_arg = None
TRACE - BlockLoweringOrder: function body function %test0(f32, f32) -> f32 system_v {
block0(v0: f32, v1: f32):
v2 = fcmp gt v0, v1
brnz v2, block1
jump block2

block1:
return v0

block2:
return v1
}

TRACE - BlockLoweringOrder: BlockLoweringOrder { lowered_order: [Orig { block: block0 }, EdgeAndOrig { pred: block0, edge_inst: inst1, succ_idx: 0, block: block1 }, EdgeAndOrig { pred: block0, edge_inst: inst2, succ_idx: 1, block: block2 }], lowered_succs: [(inst1, EdgeAndOrig { pred: block0, edge_inst: inst1, succ_idx: 0, block: block1 }), (inst2, EdgeAndOrig { pred: block0, edge_inst: inst2, succ_idx: 1, block: block2 })], lowered_succ_indices: [(inst1, Block(1)), (inst2, Block(2))], lowered_succ_ranges: [(0, 2), (2, 2), (2, 2)], orig_map: SecondaryMap { elems: [Some(Block(0)), Some(Block(1)), Some(Block(2))], default: None, unused: PhantomData }, cold_blocks: {} }
TRACE - bb block0 param v0: regs ValueRegs { parts: [v128, v2097151] }
TRACE - bb block0 param v1: regs ValueRegs { parts: [v129, v2097151] }
TRACE - bb block0 inst inst0 (FloatCompare { opcode: Fcmp, args: [v0, v1], cond: GreaterThan }): result v2 regs ValueRegs { parts: [v130, v2097151] }
TRACE - retval gets regs ValueRegs { parts: [v131, v2097151] }
TRACE - bb block0 inst inst0 has color 1
TRACE - bb block0 inst inst1 has color 1
TRACE - -> side-effecting; incrementing color for next inst
TRACE - bb block0 inst inst2 has color 2
TRACE - -> side-effecting; incrementing color for next inst
TRACE - bb block1 inst inst3 has color 4
TRACE - -> side-effecting; incrementing color for next inst
TRACE - bb block2 inst inst4 has color 6
TRACE - -> side-effecting; incrementing color for next inst
TRACE - arg v0 used, old state Unused, new Once
TRACE - arg v1 used, old state Unused, new Once
TRACE - arg v2 used, old state Unused, new Once
TRACE - arg v0 used, old state Once, new Multiple
TRACE - -> pushing args for v0 onto stack
TRACE - arg v1 used, old state Once, new Multiple
TRACE - -> pushing args for v1 onto stack
DEBUG - timing: Starting VCode lowering, (during <no pass>)
TRACE - about to lower function: function %test0(f32, f32) -> f32 system_v {
block0(v0: f32, v1: f32):
v2 = fcmp gt v0, v1
brnz v2, block1
jump block2

block1:
return v0

block2:
return v1
}

TRACE - lower_clif_block: block block2 inst inst4 (MultiAry { opcode: Return, args: EntityList { index: 17, unused: PhantomData } }) is_branch false side_effect true value_needed false
TRACE - lowering: inst inst4: MultiAry { opcode: Return, args: EntityList { index: 17, unused: PhantomData } }
TRACE - get_input_for_val: val v1 at cur_inst Some(inst4) cur_scan_entry_color Some(InstColor(6))
TRACE - put_value_in_regs: val v1
TRACE - -> regs ValueRegs { parts: [v129, v2097151] }
TRACE - emit: Mov { rd: Writable { reg: v131 }, rm: v129, ty: types::F32 }
TRACE - emit: Mov { rd: Writable { reg: p10f }, rm: v131, ty: types::F32 }
TRACE - emit: Ret
TRACE - lower_clif_block: block block1 inst inst3 (MultiAry { opcode: Return, args: EntityList { index: 13, unused: PhantomData } }) is_branch false side_effect true value_needed false
TRACE - lowering: inst inst3: MultiAry { opcode: Return, args: EntityList { index: 13, unused: PhantomData } }
TRACE - get_input_for_val: val v0 at cur_inst Some(inst3) cur_scan_entry_color Some(InstColor(4))
TRACE - put_value_in_regs: val v0
TRACE - -> regs ValueRegs { parts: [v128, v2097151] }
TRACE - emit: Mov { rd: Writable { reg: v131 }, rm: v128, ty: types::F32 }
TRACE - emit: Mov { rd: Writable { reg: p10f }, rm: v131, ty: types::F32 }
TRACE - emit: Ret
TRACE - lower_clif_branches: block block0 branches [inst1, inst2] targets [MachLabel(1), MachLabel(2)]
TRACE - put_value_in_regs: val v2
TRACE - -> regs ValueRegs { parts: [v130, v2097151] }
TRACE - emit: CondBr { taken: Label(MachLabel(1)), not_taken: Label(MachLabel(2)), kind: IntegerCompare { kind: NotEqual, rs1: v130, rs2: p0i } }
TRACE - lower_clif_block: block block0 inst inst2 (Jump { opcode: Jump, args: EntityList { index: 0, unused: PhantomData }, destination: block2 }) is_branch true side_effect true value_needed false
TRACE - lower_clif_block: block block0 inst inst1 (Branch { opcode: Brnz, args: EntityList { index: 9, unused: PhantomData }, destination: block1 }) is_branch true side_effect true value_needed false
TRACE - lower_clif_block: block block0 inst inst0 (FloatCompare { opcode: Fcmp, args: [v0, v1], cond: GreaterThan }) is_branch false side_effect false value_needed true
TRACE - lowering: inst inst0: FloatCompare { opcode: Fcmp, args: [v0, v1], cond: GreaterThan }
TRACE - get_input_for_val: val v0 at cur_inst Some(inst0) cur_scan_entry_color Some(InstColor(1))
TRACE - put_value_in_regs: val v0
TRACE - -> regs ValueRegs { parts: [v128, v2097151] }
TRACE - get_input_for_val: val v1 at cur_inst Some(inst0) cur_scan_entry_color Some(InstColor(1))
TRACE - put_value_in_regs: val v1
TRACE - -> regs ValueRegs { parts: [v129, v2097151] }
TRACE - emit: Ffcmp { rd: Writable { reg: v130 }, cc: GreaterThan, ty: types::F32, rs1: v128, rs2: v129 }
TRACE - gen_arg_setup: entry BB block0 args are:
[v0, v1]
TRACE - emit: Mov { rd: Writable { reg: v128 }, rm: p10f, ty: types::F32 }
TRACE - emit: Mov { rd: Writable { reg: v129 }, rm: p11f, ty: types::F32 }
TRACE - gen_retval_area_setup: not needed
TRACE - built vcode: VCode {
Entry block: 0
Block 0:
(original IR block: block0)
(successor: Block 1)
(successor: Block 2)
(instruction range: 0 .. 4)
Inst 0: fmv.s v128,fa0
Inst 1: fmv.s v129,fa1
Inst 2: fgt v130,v128,v129
Inst 3: bne v130,zero,taken(label1),not_taken(label2)
Block 1:
(original IR block: block1)
(instruction range: 4 .. 7)
Inst 4: fmv.s v131,v128
Inst 5: fmv.s fa0,v131
Inst 6: ret
Block 2:
(original IR block: block2)
(instruction range: 7 .. 10)
Inst 7: fmv.s v131,v129
Inst 8: fmv.s fa0,v131
Inst 9: ret
}

DEBUG - timing: Ending VCode lowering
TRACE - vcode from lowering:
VCode {
Entry block: 0
Block 0:
(original IR block: block0)
(successor: Block 1)
(successor: Block 2)
(instruction range: 0 .. 4)
Inst 0: fmv.s v128,fa0
Inst 1: fmv.s v129,fa1
Inst 2: fgt v130,v128,v129
Inst 3: bne v130,zero,taken(label1),not_taken(label2)
Block 1:
(original IR block: block1)
(instruction range: 4 .. 7)
Inst 4: fmv.s v131,v128
Inst 5: fmv.s fa0,v131
Inst 6: ret
Block 2:
(original IR block: block2)
(instruction range: 7 .. 10)
Inst 7: fmv.s v131,v129
Inst 8: fmv.s fa0,v131
Inst 9: ret
}

DEBUG - timing: Starting Register allocation, (during <no pass>)
INFO - === REGALLOC RESULTS ===
INFO - block0: [succs [1, 2] preds []]
INFO - inst0-pre: <<< start v0 in p0i (range6) (bundle4294967295)
INFO - inst0-pre: <<< start v75 in p11f (range7) (bundle4294967295)
INFO - inst0-pre: <<< start v128 in p10f (range3) (bundle0)
INFO - inst0-pre: <<< start v129 in p5f (range8) (bundle5)
INFO - inst0: op Def: v128f reg [none], Use: v74f reg [none]
INFO - inst0-post: end v129 in p5f (range8) (bundle5) >>>
INFO - inst1-pre: end v75 in p11f (range7) (bundle4294967295) >>>
INFO - inst1: op Def: v129f reg [none], Use: v75f reg [none]
INFO - inst1-post: <<< start v129 in p11f (range4) (bundle4)
INFO - inst2: op Def: v130i reg [p11i], Use: v128f reg [p10f], Use: v129f reg [p11f]
INFO - inst2-post: <<< start v130 in p11i (range5) (bundle2)
INFO - inst3: br Use: v130i reg [p11i], Use: v0i reg [p0i]
INFO - inst3-post: end v0 in p0i (range6) (bundle4294967295) >>>
INFO - inst3-post: end v130 in p11i (range5) (bundle2) >>>
INFO - block1: [succs [] preds [0]]
INFO - inst4-pre: end v129 in p11f (range4) (bundle4) >>>
INFO - inst4: op Def: v131f reg [none], Use: v128f reg [none]
INFO - inst4-post: prog-move v128 (Any) -> v131 (Any)
INFO - inst5-pre: end v128 in p10f (range3) (bundle0) >>>
INFO - inst5-pre: <<< start v131 in p10f (range2) (bundle0)
INFO - inst5: op Def: v74f reg [none], Use: v131f reg [none]
INFO - inst6-pre: end v131 in p10f (range2) (bundle0) >>>
INFO - inst6: ret
INFO - block2: [succs [] preds [0]]
INFO - inst7-pre: <<< start v129 in p11f (range1) (bundle4)
INFO - inst7: op Def: v131f reg [none], Use: v129f reg [none]
INFO - inst7-post: prog-move v129 (Any) -> v131 (Any)
INFO - inst8-pre: end v129 in p11f (range1) (bundle4) >>>
INFO - inst8-pre: <<< start v131 in p10f (range0) (bundle0)
INFO - inst8-pre: move p11f -> p10f)
INFO - inst8: op Def: v74f reg [none], Use: v131f reg [none]
INFO -
[message truncated]

Wasmtime GitHub notifications bot (May 08 2022 at 14:43):

bjorn3 commented on issue #4110:

you need integer register to implement float mov , and move single-precision an double precesion use different instruction.

You can move a double precision float in both cases, right? The riscv specification explicitly allows this AFAICT:

Software might not know the current type of data stored in a floating-point register but has to be able to save and restore the register values, hence the result of using wider operations to transfer narrower values has to be defined.

Wasmtime GitHub notifications bot (May 08 2022 at 22:53):

yuyang-ok commented on issue #4110:

thanks , I did not notice that , I will try.

Wasmtime GitHub notifications bot (May 08 2022 at 22:55):

yuyang-ok closed issue #4110:

block1:
return v0

block2:
return v1
}

block1:
return v0

block2:
return v1
}

Wasmtime GitHub notifications bot (May 09 2022 at 18:21):

cfallin commented on issue #4110:

@yuyang-ok to add a little more detail: the idea is that at regalloc time, we only deal with registers, not the types of values within registers. This is to prevent bugs: otherwise we need to track the type and get it right in all cases, we haven't historically done a perfect job of that when dealing with certain optimizations, and bugs are catastrophic (causing CVEs) when this is wrong.

So, loads, spills, and moves always deal with the whole register value. I'm surprised that RISC-V doesn't have an FP-reg-to-FP-reg move without going through an integer register; but you should be able to synthesize this by using the scratch integer register.

Also, one more thing to note: in the future, it is probably best not to copy the entire trace output of the compiler into an issue, especially without an introduction at the top; it makes it hard for contributors to see what the actual problem is and help you :-)

Last updated: Dec 23 2024 at 12:05 UTC