Stream: git-wasmtime

Topic: wasmtime / issue #4104 Cranelift: sdiv.i32x4 panics durin...


view this post on Zulip Wasmtime GitHub notifications bot (May 05 2022 at 19:47):

aweinstock314 opened issue #4104:

.clif Test Case

function u0:0() system_v {
    const0 = 0x000000280000001e000000140000000a
    const1 = 0x00000004000000030000000200000001

block0:
    v0 = vconst.i32x4 const0
    v1 = vconst.i32x4 const1
    v2 = sdiv v0, v1
    return
}

Steps to Reproduce

Script to reproduce the issue (minimized from https://gitlab.com/veloren/dev/veloren/-/blob/5c4a5908f1c996560d7d8fa68a7a1f1cffb50971/world/src/site2/gen/jit.rs#L864-919):

cranelift_sdiv_20220505.rs.txt

Expected Results

Either a sequence of instructions that perform SIMD integer division (since it seems like there's no single instruction that does so on x86_64) or a cranelift verifier error.
Hopefully the former, since sdiv is documented as working on "A scalar or vector integer type" at https://docs.rs/cranelift-codegen/latest/cranelift_codegen/ir/trait.InstBuilder.html#method.sdiv

Actual Results

In debug mode, I get

thread 'main' panicked at 'assertion failed: rc_dst == rc_src', /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/inst/mod.rs:2710:9
stack backtrace:
   0: rust_begin_unwind
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/std/src/panicking.rs:498:5
   1: core::panicking::panic_fmt
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/core/src/panicking.rs:107:14
   2: core::panicking::panic
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/core/src/panicking.rs:48:5
   3: cranelift_codegen::isa::x64::inst::<impl cranelift_codegen::machinst::MachInst for cranelift_codegen::isa::x64::lower::isle::generated_code::MInst>::gen_move
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/inst/mod.rs:2710:9
   4: cranelift_codegen::isa::x64::lower::lower_insn_to_regs
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/lower.rs:2919:22
   5: cranelift_codegen::isa::x64::lower::<impl cranelift_codegen::machinst::lower::LowerBackend for cranelift_codegen::isa::x64::X64Backend>::lower
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/lower.rs:3700:9
   6: cranelift_codegen::machinst::lower::Lower<I>::lower_clif_block
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/machinst/lower.rs:752:17
   7: cranelift_codegen::machinst::lower::Lower<I>::lower
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/machinst/lower.rs:993:17
   8: cranelift_codegen::machinst::compile::compile
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/machinst/compile.rs:31:9
   9: cranelift_codegen::isa::x64::X64Backend::compile_vcode
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/mod.rs:53:9
  10: <cranelift_codegen::isa::x64::X64Backend as cranelift_codegen::isa::TargetIsa>::compile_function
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/mod.rs:64:21
  11: cranelift_codegen::context::Context::compile
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/context.rs:165:22
  12: cranelift_codegen::context::Context::compile_and_emit
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/context.rs:115:20
  13: cranelift_sdiv_20220505_30bc7f2d1948e7bde4e87623::main
             at /home/avi/.cache/rust-script/projects/30bc7f2d1948e7bde4e87623/cranelift_sdiv_20220505.rs:64:16
  14: core::ops::function::FnOnce::call_once
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/core/src/ops/function.rs:227:5

In release mode I get

thread 'main' panicked at 'called `Option::unwrap()` on a `None` value', /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/inst/mod.rs:251:33
stack backtrace:
   0: rust_begin_unwind
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/std/src/panicking.rs:498:5
   1: core::panicking::panic_fmt
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/core/src/panicking.rs:107:14
   2: core::panicking::panic
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/core/src/panicking.rs:48:5
   3: cranelift_codegen::isa::x64::inst::<impl cranelift_codegen::machinst::MachInst for cranelift_codegen::isa::x64::lower::isle::generated_code::MInst>::gen_move
   4: cranelift_codegen::isa::x64::lower::lower_insn_to_regs
   5: cranelift_codegen::machinst::lower::Lower<I>::lower
   6: cranelift_codegen::machinst::compile::compile
   7: <cranelift_codegen::isa::x64::X64Backend as cranelift_codegen::isa::TargetIsa>::compile_function
   8: cranelift_codegen::context::Context::compile
   9: cranelift_codegen::context::Context::compile_and_emit
  10: cranelift_sdiv_20220505_30bc7f2d1948e7bde4e87623::main

Versions and Environment

Cranelift version or commit:

anyhow = "1.0"
cranelift-codegen = "0.82"
cranelift-frontend = "0.82"
target-lexicon = "0.12.3"

Operating system: Gentoo Linux (5.10.68-gentoo-dist kernel)

Architecture:

model name      : Intel(R) Core(TM) i7-10850H CPU @ 2.70GHz
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb invpcid_single ssbd ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid mpx rdseed adx smap clflushopt intel_pt xsaveopt xsavec xgetbv1 xsaves dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp pku ospke md_clear flush_l1d arch_capabilities

Extra Info

view this post on Zulip Wasmtime GitHub notifications bot (May 05 2022 at 19:47):

aweinstock314 labeled issue #4104:

.clif Test Case

function u0:0() system_v {
    const0 = 0x000000280000001e000000140000000a
    const1 = 0x00000004000000030000000200000001

block0:
    v0 = vconst.i32x4 const0
    v1 = vconst.i32x4 const1
    v2 = sdiv v0, v1
    return
}

Steps to Reproduce

Script to reproduce the issue (minimized from https://gitlab.com/veloren/dev/veloren/-/blob/5c4a5908f1c996560d7d8fa68a7a1f1cffb50971/world/src/site2/gen/jit.rs#L864-919):

cranelift_sdiv_20220505.rs.txt

Expected Results

Either a sequence of instructions that perform SIMD integer division (since it seems like there's no single instruction that does so on x86_64) or a cranelift verifier error.
Hopefully the former, since sdiv is documented as working on "A scalar or vector integer type" at https://docs.rs/cranelift-codegen/latest/cranelift_codegen/ir/trait.InstBuilder.html#method.sdiv

Actual Results

In debug mode, I get

thread 'main' panicked at 'assertion failed: rc_dst == rc_src', /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/inst/mod.rs:2710:9
stack backtrace:
   0: rust_begin_unwind
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/std/src/panicking.rs:498:5
   1: core::panicking::panic_fmt
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/core/src/panicking.rs:107:14
   2: core::panicking::panic
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/core/src/panicking.rs:48:5
   3: cranelift_codegen::isa::x64::inst::<impl cranelift_codegen::machinst::MachInst for cranelift_codegen::isa::x64::lower::isle::generated_code::MInst>::gen_move
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/inst/mod.rs:2710:9
   4: cranelift_codegen::isa::x64::lower::lower_insn_to_regs
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/lower.rs:2919:22
   5: cranelift_codegen::isa::x64::lower::<impl cranelift_codegen::machinst::lower::LowerBackend for cranelift_codegen::isa::x64::X64Backend>::lower
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/lower.rs:3700:9
   6: cranelift_codegen::machinst::lower::Lower<I>::lower_clif_block
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/machinst/lower.rs:752:17
   7: cranelift_codegen::machinst::lower::Lower<I>::lower
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/machinst/lower.rs:993:17
   8: cranelift_codegen::machinst::compile::compile
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/machinst/compile.rs:31:9
   9: cranelift_codegen::isa::x64::X64Backend::compile_vcode
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/mod.rs:53:9
  10: <cranelift_codegen::isa::x64::X64Backend as cranelift_codegen::isa::TargetIsa>::compile_function
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/mod.rs:64:21
  11: cranelift_codegen::context::Context::compile
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/context.rs:165:22
  12: cranelift_codegen::context::Context::compile_and_emit
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/context.rs:115:20
  13: cranelift_sdiv_20220505_30bc7f2d1948e7bde4e87623::main
             at /home/avi/.cache/rust-script/projects/30bc7f2d1948e7bde4e87623/cranelift_sdiv_20220505.rs:64:16
  14: core::ops::function::FnOnce::call_once
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/core/src/ops/function.rs:227:5

In release mode I get

thread 'main' panicked at 'called `Option::unwrap()` on a `None` value', /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/inst/mod.rs:251:33
stack backtrace:
   0: rust_begin_unwind
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/std/src/panicking.rs:498:5
   1: core::panicking::panic_fmt
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/core/src/panicking.rs:107:14
   2: core::panicking::panic
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/core/src/panicking.rs:48:5
   3: cranelift_codegen::isa::x64::inst::<impl cranelift_codegen::machinst::MachInst for cranelift_codegen::isa::x64::lower::isle::generated_code::MInst>::gen_move
   4: cranelift_codegen::isa::x64::lower::lower_insn_to_regs
   5: cranelift_codegen::machinst::lower::Lower<I>::lower
   6: cranelift_codegen::machinst::compile::compile
   7: <cranelift_codegen::isa::x64::X64Backend as cranelift_codegen::isa::TargetIsa>::compile_function
   8: cranelift_codegen::context::Context::compile
   9: cranelift_codegen::context::Context::compile_and_emit
  10: cranelift_sdiv_20220505_30bc7f2d1948e7bde4e87623::main

Versions and Environment

Cranelift version or commit:

anyhow = "1.0"
cranelift-codegen = "0.82"
cranelift-frontend = "0.82"
target-lexicon = "0.12.3"

Operating system: Gentoo Linux (5.10.68-gentoo-dist kernel)

Architecture:

model name      : Intel(R) Core(TM) i7-10850H CPU @ 2.70GHz
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb invpcid_single ssbd ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid mpx rdseed adx smap clflushopt intel_pt xsaveopt xsavec xgetbv1 xsaves dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp pku ospke md_clear flush_l1d arch_capabilities

Extra Info

view this post on Zulip Wasmtime GitHub notifications bot (May 05 2022 at 19:47):

aweinstock314 labeled issue #4104:

.clif Test Case

function u0:0() system_v {
    const0 = 0x000000280000001e000000140000000a
    const1 = 0x00000004000000030000000200000001

block0:
    v0 = vconst.i32x4 const0
    v1 = vconst.i32x4 const1
    v2 = sdiv v0, v1
    return
}

Steps to Reproduce

Script to reproduce the issue (minimized from https://gitlab.com/veloren/dev/veloren/-/blob/5c4a5908f1c996560d7d8fa68a7a1f1cffb50971/world/src/site2/gen/jit.rs#L864-919):

cranelift_sdiv_20220505.rs.txt

Expected Results

Either a sequence of instructions that perform SIMD integer division (since it seems like there's no single instruction that does so on x86_64) or a cranelift verifier error.
Hopefully the former, since sdiv is documented as working on "A scalar or vector integer type" at https://docs.rs/cranelift-codegen/latest/cranelift_codegen/ir/trait.InstBuilder.html#method.sdiv

Actual Results

In debug mode, I get

thread 'main' panicked at 'assertion failed: rc_dst == rc_src', /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/inst/mod.rs:2710:9
stack backtrace:
   0: rust_begin_unwind
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/std/src/panicking.rs:498:5
   1: core::panicking::panic_fmt
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/core/src/panicking.rs:107:14
   2: core::panicking::panic
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/core/src/panicking.rs:48:5
   3: cranelift_codegen::isa::x64::inst::<impl cranelift_codegen::machinst::MachInst for cranelift_codegen::isa::x64::lower::isle::generated_code::MInst>::gen_move
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/inst/mod.rs:2710:9
   4: cranelift_codegen::isa::x64::lower::lower_insn_to_regs
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/lower.rs:2919:22
   5: cranelift_codegen::isa::x64::lower::<impl cranelift_codegen::machinst::lower::LowerBackend for cranelift_codegen::isa::x64::X64Backend>::lower
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/lower.rs:3700:9
   6: cranelift_codegen::machinst::lower::Lower<I>::lower_clif_block
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/machinst/lower.rs:752:17
   7: cranelift_codegen::machinst::lower::Lower<I>::lower
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/machinst/lower.rs:993:17
   8: cranelift_codegen::machinst::compile::compile
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/machinst/compile.rs:31:9
   9: cranelift_codegen::isa::x64::X64Backend::compile_vcode
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/mod.rs:53:9
  10: <cranelift_codegen::isa::x64::X64Backend as cranelift_codegen::isa::TargetIsa>::compile_function
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/mod.rs:64:21
  11: cranelift_codegen::context::Context::compile
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/context.rs:165:22
  12: cranelift_codegen::context::Context::compile_and_emit
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/context.rs:115:20
  13: cranelift_sdiv_20220505_30bc7f2d1948e7bde4e87623::main
             at /home/avi/.cache/rust-script/projects/30bc7f2d1948e7bde4e87623/cranelift_sdiv_20220505.rs:64:16
  14: core::ops::function::FnOnce::call_once
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/core/src/ops/function.rs:227:5

In release mode I get

thread 'main' panicked at 'called `Option::unwrap()` on a `None` value', /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/inst/mod.rs:251:33
stack backtrace:
   0: rust_begin_unwind
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/std/src/panicking.rs:498:5
   1: core::panicking::panic_fmt
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/core/src/panicking.rs:107:14
   2: core::panicking::panic
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/core/src/panicking.rs:48:5
   3: cranelift_codegen::isa::x64::inst::<impl cranelift_codegen::machinst::MachInst for cranelift_codegen::isa::x64::lower::isle::generated_code::MInst>::gen_move
   4: cranelift_codegen::isa::x64::lower::lower_insn_to_regs
   5: cranelift_codegen::machinst::lower::Lower<I>::lower
   6: cranelift_codegen::machinst::compile::compile
   7: <cranelift_codegen::isa::x64::X64Backend as cranelift_codegen::isa::TargetIsa>::compile_function
   8: cranelift_codegen::context::Context::compile
   9: cranelift_codegen::context::Context::compile_and_emit
  10: cranelift_sdiv_20220505_30bc7f2d1948e7bde4e87623::main

Versions and Environment

Cranelift version or commit:

anyhow = "1.0"
cranelift-codegen = "0.82"
cranelift-frontend = "0.82"
target-lexicon = "0.12.3"

Operating system: Gentoo Linux (5.10.68-gentoo-dist kernel)

Architecture:

model name      : Intel(R) Core(TM) i7-10850H CPU @ 2.70GHz
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb invpcid_single ssbd ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid mpx rdseed adx smap clflushopt intel_pt xsaveopt xsavec xgetbv1 xsaves dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp pku ospke md_clear flush_l1d arch_capabilities

Extra Info

view this post on Zulip Wasmtime GitHub notifications bot (May 05 2022 at 20:25):

abrown commented on issue #4104:

@aweinstock314, good find! I took a look at your script to generate various patterns and it looked interesting; I'm interested in the details of what you are trying to test (something about the "interpreter vs JIT"). I had the vague thought that some of that could be integrated into Cranelift's fuzz testing but I'm not totally sure what is going on yet.

For this issue, though, this bug highlights fixes at multiple levels. First, we could add an assert/panic into the lowering of sdiv to more clearly state that this instruction is not implemented for vector types; your stack traces highlight how there is no proper error message returned. Secondly, I guess we need to decide what to do about vector sdiv:

view this post on Zulip Wasmtime GitHub notifications bot (May 05 2022 at 21:03):

aweinstock314 commented on issue #4104:

The fuzzer/proptest testing isn't directly related to how I found this bug. The overall context is that there's an interpreted language being used for procedural generation that expresses 3d shapes as compositions of simpler shapes (Constructive Solid Geometry), and when rasterizing the shapes to a voxel grid, it's faster to JIT-compile the test for "is a point contained in this shape" than to interpret the AST that represents the shape. Sdiv is being used in the Repeat instruction, which produces a shape composed of several copies of another shape along a specified vector. The fuzzer is producing random ASTs that represent shapes, and checking that the interpreter agrees with the JIT when rasterizing the shapes in a 64x64x64 volume.

I don't think I need vector sdiv necessarily: the shapes rasterize correctly with scalar division, and I'm not sure that Repeat instructions are frequent enough in actual workloads for it to be performance-critical, and if they are, it would suffice for me to translate libdivide_s32_do_vec128 or libdivide_s32_branchfree_do_vec128 to CLIF manually.

Presumably it to be handled in cranelift, you'd want to handle it for all sizes? (I guess cranelift could also lower it into extractlanes, scalar division, then insertlanes, then have optimizations for particular sizes as needed, but that would have somewhat nonintuitive performance implications).

view this post on Zulip Wasmtime GitHub notifications bot (May 05 2022 at 21:03):

bjorn3 commented on issue #4104:

Cg_clif will need it for a fast implementation of simd integer division.

view this post on Zulip Wasmtime GitHub notifications bot (May 05 2022 at 21:03):

bjorn3 edited a comment on issue #4104:

Cg_clif will need vector sdiv for a fast implementation of simd integer division.

view this post on Zulip Wasmtime GitHub notifications bot (May 06 2022 at 10:37):

akirilov-arm commented on issue #4104:

Vector integer division hasn't been implemented in the AArch64 backend because we haven't been aware of a real need for it so far (other than completeness), but we used to have a more explicit error message before the ISLE transition; now it is just the generic implemented in ISLE one. If the target supports the Scalable Vector Extension (SVE), then it is straightforward to implement for 32- and 64-bit elements (which is what this issue asks for), while 8- or 16-bit elements could be handled by vector sign- or zero-extensions and 4 or 2 32-bit divisions respectively, followed by narrowing conversions. Without SVE support, i.e. just base NEON, it becomes tricky.

view this post on Zulip Wasmtime GitHub notifications bot (May 10 2022 at 13:23):

uweigand commented on issue #4104:

On s390x we don't yet have any SIMD support, so this hasn't been an issue. Once we add SIMD, we'll have the problem that the current ISA does not actually provide any SIMD integer divide instructions, so if the back-end had to implement a vector divide, I guess we'd have to scalarize the operation manually.

view this post on Zulip Wasmtime GitHub notifications bot (May 11 2022 at 17:08):

cfallin commented on issue #4104:

Given the above (not implemented in any backend, and difficult to support with current hardware), I suspect that the right answer is to say that sdiv takes scalar types only. These are always subjective calls at some level, but I think polyfilling a non-hardware-supported operation with a more involved sequence mostly makes sense either when that sequence is a widely-accepted primitive (e.g., popcount) or is supported on all but a few hardware platforms/configurations. Here that seems not to be the case.

We can always widen our support later; perhaps we can reconsider and add a platform-independent legalization in the future. But for now it seems right to reflect the above difficulties in the opcode type restrictions.

I'm happy to do a quick PR to update the opcode definition!

view this post on Zulip Wasmtime GitHub notifications bot (May 11 2022 at 18:10):

cfallin closed issue #4104:

.clif Test Case

function u0:0() system_v {
    const0 = 0x000000280000001e000000140000000a
    const1 = 0x00000004000000030000000200000001

block0:
    v0 = vconst.i32x4 const0
    v1 = vconst.i32x4 const1
    v2 = sdiv v0, v1
    return
}

Steps to Reproduce

Script to reproduce the issue (minimized from https://gitlab.com/veloren/dev/veloren/-/blob/5c4a5908f1c996560d7d8fa68a7a1f1cffb50971/world/src/site2/gen/jit.rs#L864-919):

cranelift_sdiv_20220505.rs.txt

Expected Results

Either a sequence of instructions that perform SIMD integer division (since it seems like there's no single instruction that does so on x86_64) or a cranelift verifier error.
Hopefully the former, since sdiv is documented as working on "A scalar or vector integer type" at https://docs.rs/cranelift-codegen/latest/cranelift_codegen/ir/trait.InstBuilder.html#method.sdiv

Actual Results

In debug mode, I get

thread 'main' panicked at 'assertion failed: rc_dst == rc_src', /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/inst/mod.rs:2710:9
stack backtrace:
   0: rust_begin_unwind
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/std/src/panicking.rs:498:5
   1: core::panicking::panic_fmt
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/core/src/panicking.rs:107:14
   2: core::panicking::panic
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/core/src/panicking.rs:48:5
   3: cranelift_codegen::isa::x64::inst::<impl cranelift_codegen::machinst::MachInst for cranelift_codegen::isa::x64::lower::isle::generated_code::MInst>::gen_move
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/inst/mod.rs:2710:9
   4: cranelift_codegen::isa::x64::lower::lower_insn_to_regs
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/lower.rs:2919:22
   5: cranelift_codegen::isa::x64::lower::<impl cranelift_codegen::machinst::lower::LowerBackend for cranelift_codegen::isa::x64::X64Backend>::lower
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/lower.rs:3700:9
   6: cranelift_codegen::machinst::lower::Lower<I>::lower_clif_block
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/machinst/lower.rs:752:17
   7: cranelift_codegen::machinst::lower::Lower<I>::lower
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/machinst/lower.rs:993:17
   8: cranelift_codegen::machinst::compile::compile
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/machinst/compile.rs:31:9
   9: cranelift_codegen::isa::x64::X64Backend::compile_vcode
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/mod.rs:53:9
  10: <cranelift_codegen::isa::x64::X64Backend as cranelift_codegen::isa::TargetIsa>::compile_function
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/mod.rs:64:21
  11: cranelift_codegen::context::Context::compile
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/context.rs:165:22
  12: cranelift_codegen::context::Context::compile_and_emit
             at /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/context.rs:115:20
  13: cranelift_sdiv_20220505_30bc7f2d1948e7bde4e87623::main
             at /home/avi/.cache/rust-script/projects/30bc7f2d1948e7bde4e87623/cranelift_sdiv_20220505.rs:64:16
  14: core::ops::function::FnOnce::call_once
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/core/src/ops/function.rs:227:5

In release mode I get

thread 'main' panicked at 'called `Option::unwrap()` on a `None` value', /home/avi/.cargo/registry/src/github.com-1ecc6299db9ec823/cranelift-codegen-0.82.3/src/isa/x64/inst/mod.rs:251:33
stack backtrace:
   0: rust_begin_unwind
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/std/src/panicking.rs:498:5
   1: core::panicking::panic_fmt
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/core/src/panicking.rs:107:14
   2: core::panicking::panic
             at /rustc/91a0600a5c22b9d159e3c57526af83e71d1120f8/library/core/src/panicking.rs:48:5
   3: cranelift_codegen::isa::x64::inst::<impl cranelift_codegen::machinst::MachInst for cranelift_codegen::isa::x64::lower::isle::generated_code::MInst>::gen_move
   4: cranelift_codegen::isa::x64::lower::lower_insn_to_regs
   5: cranelift_codegen::machinst::lower::Lower<I>::lower
   6: cranelift_codegen::machinst::compile::compile
   7: <cranelift_codegen::isa::x64::X64Backend as cranelift_codegen::isa::TargetIsa>::compile_function
   8: cranelift_codegen::context::Context::compile
   9: cranelift_codegen::context::Context::compile_and_emit
  10: cranelift_sdiv_20220505_30bc7f2d1948e7bde4e87623::main

Versions and Environment

Cranelift version or commit:

anyhow = "1.0"
cranelift-codegen = "0.82"
cranelift-frontend = "0.82"
target-lexicon = "0.12.3"

Operating system: Gentoo Linux (5.10.68-gentoo-dist kernel)

Architecture:

model name      : Intel(R) Core(TM) i7-10850H CPU @ 2.70GHz
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb invpcid_single ssbd ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid mpx rdseed adx smap clflushopt intel_pt xsaveopt xsavec xgetbv1 xsaves dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp pku ospke md_clear flush_l1d arch_capabilities

Extra Info


Last updated: Dec 23 2024 at 12:05 UTC