Stream: git-wasmtime

Topic: wasmtime / issue #4070 I am trying to add risc-v backend.


view this post on Zulip Wasmtime GitHub notifications bot (Apr 26 2022 at 00:21):

yuyang-ok opened issue #4070:

here is my code.
https://github.com/yuyang-ok/wasmtime/tree/risc-v/cranelift/codegen/src/isa/risc_v

right now I have basic compile functionality.

function body function %test0(i32) -> i32 system_v {
block0(v0: i32):
brz v0, block1
jump block2

block1:
v1 = iconst.i32 1
return v1

block2:
v2 = iconst.i32 2
return v2
}

compiler to =>

VCode_Debug {
Entry block: 0
Block 0:
(successor: Block 1)
(successor: Block 2)
(instruction range: 0 .. 2)
Inst 0: Mov { rd: Writable { reg: v0J }, rm: r17J }
Inst 1: CondBr { taken: Label(MachLabel(1)), not_taken: Label(MachLabel(2)), ty: types::I32, kind: CondBrKind { kind: Equal, rs1: v0J, rs2: r57J } }
Block 1:
(instruction range: 2 .. 6)
Inst 2: AluRRImm12 { alu_op: ORI, rd: Writable { reg: v5J }, rs: r57J, imm12: Imm12 { bits: 1 } }
Inst 3: Mov { rd: Writable { reg: v3J }, rm: v5J }
Inst 4: Extend { rd: Writable { reg: r17J }, rn: v3J, signed: true, from_bits: 32, to_bits: 64 }
Inst 5: Ret
Block 2:
(instruction range: 6 .. 10)
Inst 6: AluRRImm12 { alu_op: ORI, rd: Writable { reg: v4J }, rs: r57J, imm12: Imm12 { bits: 2 } }
Inst 7: Mov { rd: Writable { reg: v3J }, rm: v4J }
Inst 8: Extend { rd: Writable { reg: r17J }, rn: v3J, signed: true, from_bits: 32, to_bits: 64 }
Inst 9: Ret
}

compile to =>

VCode_ShowWithRRU {{
Entry block: 0
Block 0:
(original IR block: block0)
(successor: Block 1)
(successor: Block 2)
(instruction range: 0 .. 4)
Inst 0: add sp,-8
Inst 1: sd fp,0(sp)
Inst 2: mov fp,sp
Inst 3: beq a0,zero,label1,label2
Block 1:
(original IR block: block1)
(instruction range: 4 .. 9)
Inst 4: ori x5,zero,1
Inst 5: sext a0,x5
Inst 6: ld fp,0(sp)
Inst 7: add sp,8
Inst 8: ret
Block 2:
(original IR block: block2)
(instruction range: 9 .. 14)
Inst 9: ori x5,zero,2
Inst 10: sext a0,x5
Inst 11: ld fp,0(sp)
Inst 12: add sp,8
Inst 13: ret
}}


view this post on Zulip Wasmtime GitHub notifications bot (Apr 26 2022 at 07:56):

yuyang-ok commented on issue #4070:

Right now , there are a lot of warnnings.
I just began this project.

view this post on Zulip Wasmtime GitHub notifications bot (Apr 26 2022 at 20:11):

cfallin commented on issue #4070:

Hi @yuyang-ok -- thank you for sharing this with us! It's really exciting that someone is tackling this project.

Right now it looks like there is a lot still left to be implemented; please let us know if you have questions about how to build something!

I think that a new backend should be considered for inclusion in-tree when it supports at least Wasm MVP, passes tests in CI (using qemu), and assuming it has a community built up around it that will participate here and help to maintain it: triage bugs, address questions and review improvements, etc. I don't mean to discourage you at all; I just want to describe what the "next steps" might look like and what will eventually need to exist. In the meantime, best of luck and let us know how we can help.

view this post on Zulip Wasmtime GitHub notifications bot (Apr 26 2022 at 23:34):

yuyang-ok commented on issue #4070:

yes. this is just a notice for someone want to do the risc-v backend too . avoid repeat work.

view this post on Zulip Wasmtime GitHub notifications bot (Apr 26 2022 at 23:34):

yuyang-ok closed issue #4070:

here is my code.
https://github.com/yuyang-ok/wasmtime/tree/risc-v/cranelift/codegen/src/isa/risc_v

right now I have basic compile functionality.

function body function %test0(i32) -> i32 system_v {
block0(v0: i32):
brz v0, block1
jump block2

block1:
v1 = iconst.i32 1
return v1

block2:
v2 = iconst.i32 2
return v2
}

compiler to =>

VCode_Debug {
Entry block: 0
Block 0:
(successor: Block 1)
(successor: Block 2)
(instruction range: 0 .. 2)
Inst 0: Mov { rd: Writable { reg: v0J }, rm: r17J }
Inst 1: CondBr { taken: Label(MachLabel(1)), not_taken: Label(MachLabel(2)), ty: types::I32, kind: CondBrKind { kind: Equal, rs1: v0J, rs2: r57J } }
Block 1:
(instruction range: 2 .. 6)
Inst 2: AluRRImm12 { alu_op: ORI, rd: Writable { reg: v5J }, rs: r57J, imm12: Imm12 { bits: 1 } }
Inst 3: Mov { rd: Writable { reg: v3J }, rm: v5J }
Inst 4: Extend { rd: Writable { reg: r17J }, rn: v3J, signed: true, from_bits: 32, to_bits: 64 }
Inst 5: Ret
Block 2:
(instruction range: 6 .. 10)
Inst 6: AluRRImm12 { alu_op: ORI, rd: Writable { reg: v4J }, rs: r57J, imm12: Imm12 { bits: 2 } }
Inst 7: Mov { rd: Writable { reg: v3J }, rm: v4J }
Inst 8: Extend { rd: Writable { reg: r17J }, rn: v3J, signed: true, from_bits: 32, to_bits: 64 }
Inst 9: Ret
}

compile to =>

VCode_ShowWithRRU {{
Entry block: 0
Block 0:
(original IR block: block0)
(successor: Block 1)
(successor: Block 2)
(instruction range: 0 .. 4)
Inst 0: add sp,-8
Inst 1: sd fp,0(sp)
Inst 2: mov fp,sp
Inst 3: beq a0,zero,label1,label2
Block 1:
(original IR block: block1)
(instruction range: 4 .. 9)
Inst 4: ori x5,zero,1
Inst 5: sext a0,x5
Inst 6: ld fp,0(sp)
Inst 7: add sp,8
Inst 8: ret
Block 2:
(original IR block: block2)
(instruction range: 9 .. 14)
Inst 9: ori x5,zero,2
Inst 10: sext a0,x5
Inst 11: ld fp,0(sp)
Inst 12: add sp,8
Inst 13: ret
}}


view this post on Zulip Wasmtime GitHub notifications bot (Apr 27 2022 at 11:02):

akirilov-arm commented on issue #4070:

In that case we should probably link issue #2217 here.

view this post on Zulip Wasmtime GitHub notifications bot (May 03 2022 at 09:40):

a1phyr commented on issue #4070:

Woah, this is neat ! Maybe you could open a draft PR to make it easier to follow your work ?


Last updated: Oct 23 2024 at 20:03 UTC