fitzgen opened issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [ ]
Opcode::Clz- [ ]
Opcode::Ctz- [ ]
Opcode::Popcnt- [ ]
Opcode::Bitrev- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Uextend- [ ]
Opcode::Sextend- [ ]
Opcode::Breduce- [ ]
Opcode::Bextend- [ ]
Opcode::Ireduce- [ ]
Opcode::Bint- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Uload8x8Complex- [ ]
Opcode::Sload8x8Complex- [ ]
Opcode::Uload16x4Complex- [ ]
Opcode::Sload16x4Complex- [ ]
Opcode::Uload32x2Complex- [ ]
Opcode::Sload32x2Complex- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::StackAddr- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Bitselect- [ ]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
fitzgen labeled issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [ ]
Opcode::Clz- [ ]
Opcode::Ctz- [ ]
Opcode::Popcnt- [ ]
Opcode::Bitrev- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Uextend- [ ]
Opcode::Sextend- [ ]
Opcode::Breduce- [ ]
Opcode::Bextend- [ ]
Opcode::Ireduce- [ ]
Opcode::Bint- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Uload8x8Complex- [ ]
Opcode::Sload8x8Complex- [ ]
Opcode::Uload16x4Complex- [ ]
Opcode::Sload16x4Complex- [ ]
Opcode::Uload32x2Complex- [ ]
Opcode::Sload32x2Complex- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::StackAddr- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Bitselect- [ ]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
fitzgen labeled issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [ ]
Opcode::Clz- [ ]
Opcode::Ctz- [ ]
Opcode::Popcnt- [ ]
Opcode::Bitrev- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Uextend- [ ]
Opcode::Sextend- [ ]
Opcode::Breduce- [ ]
Opcode::Bextend- [ ]
Opcode::Ireduce- [ ]
Opcode::Bint- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Uload8x8Complex- [ ]
Opcode::Sload8x8Complex- [ ]
Opcode::Uload16x4Complex- [ ]
Opcode::Sload16x4Complex- [ ]
Opcode::Uload32x2Complex- [ ]
Opcode::Sload32x2Complex- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::StackAddr- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Bitselect- [ ]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
fitzgen labeled issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [ ]
Opcode::Clz- [ ]
Opcode::Ctz- [ ]
Opcode::Popcnt- [ ]
Opcode::Bitrev- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Uextend- [ ]
Opcode::Sextend- [ ]
Opcode::Breduce- [ ]
Opcode::Bextend- [ ]
Opcode::Ireduce- [ ]
Opcode::Bint- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Uload8x8Complex- [ ]
Opcode::Sload8x8Complex- [ ]
Opcode::Uload16x4Complex- [ ]
Opcode::Sload16x4Complex- [ ]
Opcode::Uload32x2Complex- [ ]
Opcode::Sload32x2Complex- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::StackAddr- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Bitselect- [ ]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
fitzgen labeled issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [ ]
Opcode::Clz- [ ]
Opcode::Ctz- [ ]
Opcode::Popcnt- [ ]
Opcode::Bitrev- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Uextend- [ ]
Opcode::Sextend- [ ]
Opcode::Breduce- [ ]
Opcode::Bextend- [ ]
Opcode::Ireduce- [ ]
Opcode::Bint- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Uload8x8Complex- [ ]
Opcode::Sload8x8Complex- [ ]
Opcode::Uload16x4Complex- [ ]
Opcode::Sload16x4Complex- [ ]
Opcode::Uload32x2Complex- [ ]
Opcode::Sload32x2Complex- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::StackAddr- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Bitselect- [ ]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
fitzgen labeled issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [ ]
Opcode::Clz- [ ]
Opcode::Ctz- [ ]
Opcode::Popcnt- [ ]
Opcode::Bitrev- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Uextend- [ ]
Opcode::Sextend- [ ]
Opcode::Breduce- [ ]
Opcode::Bextend- [ ]
Opcode::Ireduce- [ ]
Opcode::Bint- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Uload8x8Complex- [ ]
Opcode::Sload8x8Complex- [ ]
Opcode::Uload16x4Complex- [ ]
Opcode::Sload16x4Complex- [ ]
Opcode::Uload32x2Complex- [ ]
Opcode::Sload32x2Complex- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::StackAddr- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Bitselect- [ ]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
github-actions[bot] commented on issue #3713:
Subscribe to Label Action
cc @cfallin, @fitzgen
<details>
This issue or pull request has been labeled: "isle"Thus the following users have been cc'd because of the following labels:
- cfallin: isle
- fitzgen: isle
To subscribe or unsubscribe from this label, edit the <code>.github/subscribe-to-label.json</code> configuration file.
Learn more.
</details>
uweigand commented on issue #3713:
I'm looking into the remaining issues on s390x. Specifically, I already have patches for branches and traps, which I'll submit shortly. For calls and returns, the issues really are cross-platform - I suspect we'll have to move those to ISLE for all targets at the same time ...
For reference, here's the list of issues I've noticed:
- For traps, the only problem is that (some) traps need to be emitted as safepoints, and there is currently no common-code mechanism to emit safepoints from ISLE. (I notice that a few traps were moved to ISLE on x64 - but they're simply no longer safepoints now, which looks like a bug to me ...) This is straightforward to fix by having the ISLE code hold on to tuples of (instruction, is_safepoint) instead of just instructions, similar to what is already done elsewhere. I have a patch for that.
- For branches, there are two problems. The first is a straightforward bug in
clif.islefixed here: https://github.com/bytecodealliance/wasmtime/pull/3718 . The second is more interesting. Currently, branches are emitted via special logic inlower_branch_group, which gets two list of branches and branch targets as input. The list of branches is not a problem; we only ever emit the first branch of that group, and that can be passed to ISLE just like any other instruction. However, when emitting the branch as machine instruction, we need to use the proper branch targets. There is currently no way to access this in ISLE, and I see no obvious way to pass this list into the ISLE machinery either. I have a patch to make this work by having the branch target list instead be generated when needed via an ISLE constructor calling a new context callbackcurrent_block_branch_targets. This works for me, but has the drawback that the context now needs to keep new global state identifying the _current block_ being emitted. (But maybe that's not really a problem, given that there is already global state identifying the current _instruction_ anyway?)- For both calls and returns, the first issue is that these fundamentally receive variable-argument lists as inputs, and need some way to iterate over these lists in ISLE. These lists are currently represented via a
ValueSlicedata type, but it turns out this doesn't work at all: any use of aValueSliceargument in ISLE code will cause the generated Rust code to fail to compile with borrow-checker errors. This is because every single generated constructor and extractor takes a mutable borrow on the context via a&mut selfargument - and theValueSlicetype refers to context memory and therefore extends the lifetime of that mutable borrow of any constructor or extractor that returns a variable of that type, which means that while aValueSlicevariable is live, no other constructor or extractor can ever be called, making it quite useless. (This would also be a problem when handling other variable-argument opcodes likeload_complex.) I have an experimental patch that uses a pair of aValueListidentifier and an integer offset into the list instead of theValueSlice, which seems to fix this - not sure if this is the preferred solution. With that patch, I can successfully handle returns.- For calls, there are still more fundamental problems. The current code delegates most of the actual instruction emission for calls to the
ABICallertrait and associated implementation (which calls back into target code to get ABI details). This code just usesctx.emitall over the place. Therefore, it is not really usable as part of CLIF processing e.g. via constructors, because CLIF separately buffers instructions, and mixing CLIFemit_insnand contextctx.emitscrambles the sequence (and also confuses the CLIF register mapper because it no longer sees everything). I think the straightforward fix would be to change theABICallerimplementation to emit CLIF instructions instead - but that likely means that all targets have to move calls to ISLE at the same time. (I do not have a patch for this.)
sparker-arm commented on issue #3713:
I'm picking up AtomicRMW for AArch64.
fitzgen edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [ ]
Opcode::Clz- [ ]
Opcode::Ctz- [ ]
Opcode::Popcnt- [ ]
Opcode::Bitrev- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Uextend- [ ]
Opcode::Sextend- [ ]
Opcode::Breduce- [ ]
Opcode::Bextend- [ ]
Opcode::Ireduce- [ ]
Opcode::Bint- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Uload8x8Complex- [ ]
Opcode::Sload8x8Complex- [ ]
Opcode::Uload16x4Complex- [ ]
Opcode::Sload16x4Complex- [ ]
Opcode::Uload32x2Complex- [ ]
Opcode::Sload32x2Complex- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::StackAddr- [ ]
Opcode::AtomicRmw(@sparker-arm)- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Bitselect- [ ]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
cfallin commented on issue #3713:
I'm going to start working down the
x86_64opcode list from the top -- clz/btz/popcnt/bitrev to start, I think. @abrown let me know what your next plans are and we can make sure not to duplicate work!
cfallin edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [ ]
Opcode::Ctz- [ ]
Opcode::Popcnt- [ ]
Opcode::Bitrev- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Uextend- [ ]
Opcode::Sextend- [ ]
Opcode::Breduce- [ ]
Opcode::Bextend- [ ]
Opcode::Ireduce- [ ]
Opcode::Bint- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Uload8x8Complex- [ ]
Opcode::Sload8x8Complex- [ ]
Opcode::Uload16x4Complex- [ ]
Opcode::Sload16x4Complex- [ ]
Opcode::Uload32x2Complex- [ ]
Opcode::Sload32x2Complex- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::StackAddr- [ ]
Opcode::AtomicRmw(@sparker-arm)- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Bitselect- [ ]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
cfallin edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [ ]
Opcode::Popcnt- [ ]
Opcode::Bitrev- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Uextend- [ ]
Opcode::Sextend- [ ]
Opcode::Breduce- [ ]
Opcode::Bextend- [ ]
Opcode::Ireduce- [ ]
Opcode::Bint- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Uload8x8Complex- [ ]
Opcode::Sload8x8Complex- [ ]
Opcode::Uload16x4Complex- [ ]
Opcode::Sload16x4Complex- [ ]
Opcode::Uload32x2Complex- [ ]
Opcode::Sload32x2Complex- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::StackAddr- [ ]
Opcode::AtomicRmw(@sparker-arm)- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Bitselect- [ ]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
cfallin edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Uload8x8Complex- [ ]
Opcode::Sload8x8Complex- [ ]
Opcode::Uload16x4Complex- [ ]
Opcode::Sload16x4Complex- [ ]
Opcode::Uload32x2Complex- [ ]
Opcode::Sload32x2Complex- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::StackAddr- [ ]
Opcode::AtomicRmw(@sparker-arm)- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Bitselect- [ ]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
abrown commented on issue #3713:
Just for the record, I am working on x64's
icmp,fcmpandselectinstructions.
jlb6740 commented on issue #3713:
Thanks @abrown. @abrown @cfallin for the record, I'd like to get started with something simple. I'd like to claim fabs and fneg.
jlb6740 edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Uload8x8Complex- [ ]
Opcode::Sload8x8Complex- [ ]
Opcode::Uload16x4Complex- [ ]
Opcode::Sload16x4Complex- [ ]
Opcode::Uload32x2Complex- [ ]
Opcode::Sload32x2Complex- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::StackAddr- [ ]
Opcode::AtomicRmw(@sparker-arm)- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Bitselect- [ ]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [x]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
jlb6740 edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Uload8x8Complex- [ ]
Opcode::Sload8x8Complex- [ ]
Opcode::Uload16x4Complex- [ ]
Opcode::Sload16x4Complex- [ ]
Opcode::Uload32x2Complex- [ ]
Opcode::Sload32x2Complex- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::StackAddr- [ ]
Opcode::AtomicRmw(@sparker-arm)- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Bitselect- [ ]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
abrown edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Uload8x8Complex- [ ]
Opcode::Sload8x8Complex- [ ]
Opcode::Uload16x4Complex- [ ]
Opcode::Sload16x4Complex- [ ]
Opcode::Uload32x2Complex- [ ]
Opcode::Sload32x2Complex- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::StackAddr- [ ]
Opcode::AtomicRmw(@sparker-arm)- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Bitselect- [ ]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
abrown edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Uload8x8Complex- [ ]
Opcode::Sload8x8Complex- [ ]
Opcode::Uload16x4Complex- [ ]
Opcode::Sload16x4Complex- [ ]
Opcode::Uload32x2Complex- [ ]
Opcode::Sload32x2Complex- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::StackAddr- [ ]
Opcode::AtomicRmw(@sparker-arm)- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Bitselect- [ ]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
abrown edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Uload8x8Complex- [ ]
Opcode::Sload8x8Complex- [ ]
Opcode::Uload16x4Complex- [ ]
Opcode::Sload16x4Complex- [ ]
Opcode::Uload32x2Complex- [ ]
Opcode::Sload32x2Complex- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::StackAddr- [ ]
Opcode::AtomicRmw(@sparker-arm)- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Bitselect- [ ]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
abrown commented on issue #3713:
I'm looking at loads and stores next, FYI.
akirilov-arm labeled issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Uload8x8Complex- [ ]
Opcode::Sload8x8Complex- [ ]
Opcode::Uload16x4Complex- [ ]
Opcode::Sload16x4Complex- [ ]
Opcode::Uload32x2Complex- [ ]
Opcode::Sload32x2Complex- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::StackAddr- [ ]
Opcode::AtomicRmw(@sparker-arm)- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Bitselect- [ ]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
abrown edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Uload8x8Complex- [ ]
Opcode::Sload8x8Complex- [ ]
Opcode::Uload16x4Complex- [ ]
Opcode::Sload16x4Complex- [ ]
Opcode::Uload32x2Complex- [ ]
Opcode::Sload32x2Complex- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::StackAddr- [ ]
Opcode::AtomicRmw(@sparker-arm)- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Bitselect- [ ]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
abrown edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::LoadComplex- [ ]
Opcode::Uload8Complex- [ ]
Opcode::Sload8Complex- [ ]
Opcode::Uload16Complex- [ ]
Opcode::Sload16Complex- [ ]
Opcode::Uload32Complex- [ ]
Opcode::Sload32Complex- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Uload8x8Complex- [ ]
Opcode::Sload8x8Complex- [ ]
Opcode::Uload16x4Complex- [ ]
Opcode::Sload16x4Complex- [ ]
Opcode::Uload32x2Complex- [ ]
Opcode::Sload32x2Complex- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StoreComplex- [ ]
Opcode::Istore8Complex- [ ]
Opcode::Istore16Complex- [ ]
Opcode::Istore32Complex- [ ]
Opcode::StackAddr- [ ]
Opcode::AtomicRmw(@sparker-arm)- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Bitselect- [ ]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
abrown edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [ ]
Opcode::AtomicRmw(@sparker-arm)- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Bitselect- [ ]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [ ]
Opcode::AtomicRmw(@sparker-arm)- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [ ]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [ ]
Opcode::AtomicRmw(@sparker-arm)- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
sparker-arm commented on issue #3713:
I'm picking up AtomicCas and IaddPairwise for aarch64.
cfallin commented on issue #3713:
@abrown are you still planning to take a look at stores on x64? I'm happy to take those first thing Mon if you haven't started yet, as I've got some isel improvements I want to do that involve them (load-op-store patterns). If you're close then no worries though!
abrown commented on issue #3713:
Well, I haven't started stores yet... so take them if you want to!
cfallin edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
cfallin edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [ ]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [ ]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [ ]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
sparker-arm commented on issue #3713:
I've also picked up snarrow, unarrow, uunarrow and fvdemote.
cfallin edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [ ]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
cfallin edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
sparker-arm commented on issue #3713:
I've started on icmp, which doesn't look like it's going to be fun!
abrown edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
abrown edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
abrown edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [ ]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [ ]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [ ]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
elliottt commented on issue #3713:
I've finished up translating icmp for x64
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [ ]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [ ]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [ ]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [ ]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [x]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [x]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x
<details>
- [ ] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
uweigand commented on issue #3713:
Transition to ISLE is now complete for s390x. All opcodes are now lowered via ISLE.
fitzgen edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [x]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x
<details>
- [x] Calls
- [ ] Returns
- [ ] Traps
- [ ] Branches
</details>
fitzgen edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [x]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x
<details>
- [x] Calls
- [x] Returns
- [ ] Traps
- [ ] Branches
</details>
fitzgen edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [x]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [ ] Branches
</details>
fitzgen edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [x]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
fitzgen edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [ ]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [x]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
sparker-arm commented on issue #3713:
I've made a PR for the aarch64 min/max instructions
afonso360 commented on issue #3713:
Last week we also merged
bmask/bextend/ireduce/breducefor aarch64
dheaton-arm commented on issue #3713:
I've picked up
iabsfor aarch64.
dheaton-arm edited a comment on issue #3713:
And also picked up
swizzleandscalartovector.Edit: also planning to do
fadd,fsub,fmul,fdiv,fmin,fmax, and the pseudo variants of the last two.
dheaton-arm edited a comment on issue #3713:
And also picked up
swizzleandscalartovector.Edit: also planning to do
fadddown tofma.
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [ ]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [x]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [x]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [ ]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [x]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [x]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [x]
Opcode::Swizzle- [ ]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [x]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [ ]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [ ]
Opcode::Fadd- [ ]
Opcode::Fsub- [ ]
Opcode::Fmul- [ ]
Opcode::Fdiv- [ ]
Opcode::Fmin- [ ]
Opcode::Fmax- [ ]
Opcode::FminPseudo- [ ]
Opcode::FmaxPseudo- [ ]
Opcode::Sqrt- [ ]
Opcode::Fneg- [ ]
Opcode::Fabs- [ ]
Opcode::Fpromote- [ ]
Opcode::Fdemote- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Trunc- [ ]
Opcode::Nearest- [ ]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw(@sparker-arm)- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [x]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [ ]
Opcode::Imax- [ ]
Opcode::Umax- [ ]
Opcode::Umin- [ ]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [ ]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [x]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [ ]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [ ]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [ ]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [ ]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [ ]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [ ]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt commented on issue #3713:
I'm working on finishing the x64 migration to ISLE. Feel free to grab instructions if you'd like to work on them, otherwise I'll continue working down the list.
sparker-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [ ]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
sparker-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
sparker-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [ ]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
sparker-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
sparker-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [ ]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [ ]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [ ]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::SwidenLow- [ ]
Opcode::Snarrow- [ ]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [ ]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [ ]
Opcode::Bitcast- [ ]
Opcode::Fabs- [ ]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [ ]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [ ]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [ ]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [ ]
Opcode::Fcopysign- [ ]
Opcode::FcvtToUint- [ ]
Opcode::FcvtToSint- [ ]
Opcode::FcvtFromUint- [ ]
Opcode::FcvtFromSint- [ ]
Opcode::FcvtToUintSat- [ ]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [ ]
Opcode::SwidenLow- [ ]
Opcode::SwidenHigh- [ ]
Opcode::UwidenLow- [ ]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [ ]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [ ]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [ ]
Opcode::Fcopysign- [ ]
Opcode::Ceil- [ ]
Opcode::Floor- [ ]
Opcode::Nearest- [ ]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [x]
Opcode::Fcopysign- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Nearest- [x]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [x]
Opcode::Fcopysign- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Nearest- [x]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [ ]
Opcode::Udiv- [ ]
Opcode::Urem- [ ]
Opcode::Sdiv- [ ]
Opcode::Srem- [ ]
Opcode::Umulhi- [ ]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [ ]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [x]
Opcode::Fcopysign- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Nearest- [x]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [x]
Opcode::Udiv- [x]
Opcode::Urem- [x]
Opcode::Sdiv- [x]
Opcode::Srem- [x]
Opcode::Umulhi- [x]
Opcode::Smulhi- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [ ]
Opcode::Vconst- [ ]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [x]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [x]
Opcode::Fcopysign- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Nearest- [x]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [x]
Opcode::Udiv- [x]
Opcode::Urem- [x]
Opcode::Sdiv- [x]
Opcode::Srem- [x]
Opcode::Umulhi- [x]
Opcode::Smulhi- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [ ]
Opcode::Shuffle- [ ]
Opcode::Swizzle- [x]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [x]
Opcode::Fcopysign- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Nearest- [x]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [x]
Opcode::Udiv- [x]
Opcode::Urem- [x]
Opcode::Sdiv- [x]
Opcode::Srem- [x]
Opcode::Umulhi- [x]
Opcode::Smulhi- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [ ]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
cfallin commented on issue #3713:
@dheaton-arm I'm planning to help push the aarch64 work to completion; I'm hoping to tackle some of the trickier remaining ones (loads and stores, with amode lowering; calls; branches; icmp/fcmp and flags users). Is that OK or have you already started on some of these?
cfallin edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [x]
Opcode::Fcopysign- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Nearest- [x]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [x]
Opcode::Udiv- [x]
Opcode::Urem- [x]
Opcode::Sdiv- [x]
Opcode::Srem- [x]
Opcode::Umulhi- [x]
Opcode::Smulhi- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [x]
Opcode::Breduce- [ ]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
cfallin edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [x]
Opcode::Fcopysign- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Nearest- [x]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [x]
Opcode::Udiv- [x]
Opcode::Urem- [x]
Opcode::Sdiv- [x]
Opcode::Srem- [x]
Opcode::Umulhi- [x]
Opcode::Smulhi- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [x]
Opcode::Breduce- [x]
Opcode::Ireduce- [ ]
Opcode::Bextend- [ ]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
cfallin edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [x]
Opcode::Fcopysign- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Nearest- [x]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [x]
Opcode::Udiv- [x]
Opcode::Urem- [x]
Opcode::Sdiv- [x]
Opcode::Srem- [x]
Opcode::Umulhi- [x]
Opcode::Smulhi- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [x]
Opcode::Breduce- [x]
Opcode::Ireduce- [x]
Opcode::Bextend- [x]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [ ]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote- [ ] Branches
</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
dheaton-arm commented on issue #3713:
I've already started on icmp and fcmp, but everything you've mentioned before those should be fine.
akirilov-arm commented on issue #3713:
@cfallin I have an upcoming patch that moves the
AModeenum definition to ISLE, but I don't plan to touch the actual lowering rules for loads and stores. We already have theamodehelper in ISLE, so the latter bit should be doable without waiting for my patch to land (of course,AModelowering itself would depend on it).My patch changes quite a lot of code because, as far as I can tell, enum definitions in ISLE always result in enums with named fields, while the existing
AModeenum has unnamed fields.
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [x]
Opcode::Fcopysign- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Nearest- [x]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [x]
Opcode::Udiv- [x]
Opcode::Urem- [x]
Opcode::Sdiv- [x]
Opcode::Srem- [x]
Opcode::Umulhi- [x]
Opcode::Smulhi- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [x]
Opcode::Breduce- [x]
Opcode::Ireduce- [x]
Opcode::Bextend- [x]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [ ]
Opcode::FcvtLowFromSint- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote- [ ] Branches
</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [x]
Opcode::Fcopysign- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Nearest- [x]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [x]
Opcode::Udiv- [x]
Opcode::Urem- [x]
Opcode::Sdiv- [x]
Opcode::Srem- [x]
Opcode::Umulhi- [x]
Opcode::Smulhi- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [x]
Opcode::Breduce- [x]
Opcode::Ireduce- [x]
Opcode::Bextend- [x]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [ ]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote- [ ] Branches
</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [x]
Opcode::Fcopysign- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Nearest- [x]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [x]
Opcode::Udiv- [x]
Opcode::Urem- [x]
Opcode::Sdiv- [x]
Opcode::Srem- [x]
Opcode::Umulhi- [x]
Opcode::Smulhi- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Insertlane- [ ]
Opcode::Extractlane- [ ]
Opcode::ScalarToVector- [ ]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [x]
Opcode::Breduce- [x]
Opcode::Ireduce- [x]
Opcode::Bextend- [x]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote- [ ] Branches
</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [x]
Opcode::Fcopysign- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Nearest- [x]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [x]
Opcode::Udiv- [x]
Opcode::Urem- [x]
Opcode::Sdiv- [x]
Opcode::Srem- [x]
Opcode::Umulhi- [x]
Opcode::Smulhi- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Insertlane- [x]
Opcode::Extractlane- [x]
Opcode::ScalarToVector- [x]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [x]
Opcode::Breduce- [x]
Opcode::Ireduce- [x]
Opcode::Bextend- [x]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [ ]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote- [ ] Branches
</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
cfallin commented on issue #3713:
OK great, I'll take loads/stores themselves, calls, and branches. Lowering of flags-using instructions will intersect with how we do icmp/fcmp so I'll hold off on those. Thanks!
My patch changes quite a lot of code because, as far as I can tell, enum definitions in ISLE always result in enums with named fields, while the existing AMode enum has unnamed fields.
Yep, but there's no fundamental reason for that, it was just a "build it as we need it" sort of thing. We could look at supporting unnamed-field enum variants if it's simpler; it would probably be a 1-2 day refactor.
cfallin edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [x]
Opcode::Fcopysign- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Nearest- [x]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [x]
Opcode::Udiv- [x]
Opcode::Urem- [x]
Opcode::Sdiv- [x]
Opcode::Srem- [x]
Opcode::Umulhi- [x]
Opcode::Smulhi- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Insertlane- [x]
Opcode::Extractlane- [x]
Opcode::ScalarToVector- [x]
Opcode::Splat- [ ]
Opcode::VanyTrue- [ ]
Opcode::VallTrue- [ ]
Opcode::VhighBits- [ ]
Opcode::Iconcat- [ ]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [x]
Opcode::Breduce- [x]
Opcode::Ireduce- [x]
Opcode::Bextend- [x]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [x]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote- [ ] Branches
</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
cfallin commented on issue #3713:
Put up PRs for call/ret and loads/stores today; the remaining instructions on aarch64 that don't depend on flags or pattern-matching with icmp/fcmp somehow are:
- GetPinnedReg/SetPinnedReg
- ExtractLane/InsertLane
- StackAddr
- IaddIfcout
- TlsValue
I'm happy to do all of these tomorrow, unless someone else objects or has partial work here, then I can do the branch and flags-related ones (trueif/trueff, selectif/selectff/select, brif/brff/brz/brnz) once @dheaton-arm 's icmp/fcmp work is done.
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [x]
Opcode::Fcopysign- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Nearest- [x]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [x]
Opcode::Udiv- [x]
Opcode::Urem- [x]
Opcode::Sdiv- [x]
Opcode::Srem- [x]
Opcode::Umulhi- [x]
Opcode::Smulhi- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Insertlane- [x]
Opcode::Extractlane- [x]
Opcode::ScalarToVector- [x]
Opcode::Splat- [x]
Opcode::VanyTrue- [x]
Opcode::VallTrue- [x]
Opcode::VhighBits- [x]
Opcode::Iconcat- [x]
Opcode::Isplit- [ ]
Opcode::TlsValue- [ ]
Opcode::SqmulRoundSat- [ ]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [x]
Opcode::Breduce- [x]
Opcode::Ireduce- [x]
Opcode::Bextend- [x]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [x]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote- [ ] Branches
</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64 -- DONE!
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [x]
Opcode::Fcopysign- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Nearest- [x]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [x]
Opcode::Udiv- [x]
Opcode::Urem- [x]
Opcode::Sdiv- [x]
Opcode::Srem- [x]
Opcode::Umulhi- [x]
Opcode::Smulhi- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Insertlane- [x]
Opcode::Extractlane- [x]
Opcode::ScalarToVector- [x]
Opcode::Splat- [x]
Opcode::VanyTrue- [x]
Opcode::VallTrue- [x]
Opcode::VhighBits- [x]
Opcode::Iconcat- [x]
Opcode::Isplit- [x]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSat- [x]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [x]
Opcode::Breduce- [x]
Opcode::Ireduce- [x]
Opcode::Bextend- [x]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [x]
Opcode::FallthroughReturn- [ ]
Opcode::Return- [ ]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote- [ ] Branches
</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
elliottt commented on issue #3713:
The x86_64 backend has been migrated to ISLE :tada:
cfallin edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64 -- DONE!
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [x]
Opcode::Fcopysign- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Nearest- [x]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [x]
Opcode::Udiv- [x]
Opcode::Urem- [x]
Opcode::Sdiv- [x]
Opcode::Srem- [x]
Opcode::Umulhi- [x]
Opcode::Smulhi- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Insertlane- [x]
Opcode::Extractlane- [x]
Opcode::ScalarToVector- [x]
Opcode::Splat- [x]
Opcode::VanyTrue- [x]
Opcode::VallTrue- [x]
Opcode::VhighBits- [x]
Opcode::Iconcat- [x]
Opcode::Isplit- [x]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSat- [x]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [x]
Opcode::Breduce- [x]
Opcode::Ireduce- [x]
Opcode::Bextend- [x]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [ ]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [ ]
Opcode::Call- [ ]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote- [ ] Branches
</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
cfallin edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64 -- DONE!
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [x]
Opcode::Fcopysign- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Nearest- [x]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [x]
Opcode::Udiv- [x]
Opcode::Urem- [x]
Opcode::Sdiv- [x]
Opcode::Srem- [x]
Opcode::Umulhi- [x]
Opcode::Smulhi- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Insertlane- [x]
Opcode::Extractlane- [x]
Opcode::ScalarToVector- [x]
Opcode::Splat- [x]
Opcode::VanyTrue- [x]
Opcode::VallTrue- [x]
Opcode::VhighBits- [x]
Opcode::Iconcat- [x]
Opcode::Isplit- [x]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSat- [x]
Opcode::Uunarrow</details>
aarch64
<details>
- [ ]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [x]
Opcode::Breduce- [x]
Opcode::Ireduce- [x]
Opcode::Bextend- [x]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [ ]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote- [ ] Branches
</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
cfallin edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64 -- DONE!
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [x]
Opcode::Fcopysign- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Nearest- [x]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [x]
Opcode::Udiv- [x]
Opcode::Urem- [x]
Opcode::Sdiv- [x]
Opcode::Srem- [x]
Opcode::Umulhi- [x]
Opcode::Smulhi- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Insertlane- [x]
Opcode::Extractlane- [x]
Opcode::ScalarToVector- [x]
Opcode::Splat- [x]
Opcode::VanyTrue- [x]
Opcode::VallTrue- [x]
Opcode::VhighBits- [x]
Opcode::Iconcat- [x]
Opcode::Isplit- [x]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSat- [x]
Opcode::Uunarrow</details>
aarch64
<details>
- [x]
Opcode::Load- [ ]
Opcode::Uload8- [ ]
Opcode::Sload8- [ ]
Opcode::Uload16- [ ]
Opcode::Sload16- [ ]
Opcode::Uload32- [ ]
Opcode::Sload32- [ ]
Opcode::Sload8x8- [ ]
Opcode::Uload8x8- [ ]
Opcode::Sload16x4- [ ]
Opcode::Uload16x4- [ ]
Opcode::Sload32x2- [ ]
Opcode::Uload32x2- [ ]
Opcode::Store- [ ]
Opcode::Istore8- [ ]
Opcode::Istore16- [ ]
Opcode::Istore32- [ ]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [x]
Opcode::Breduce- [x]
Opcode::Ireduce- [x]
Opcode::Bextend- [x]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [ ]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [ ]
Opcode::GetPinnedReg- [ ]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [ ]
Opcode::Extractlane- [ ]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [ ]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote- [ ] Branches
</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
cfallin edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64 -- DONE!
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [x]
Opcode::Fcopysign- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Nearest- [x]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [x]
Opcode::Udiv- [x]
Opcode::Urem- [x]
Opcode::Sdiv- [x]
Opcode::Srem- [x]
Opcode::Umulhi- [x]
Opcode::Smulhi- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Insertlane- [x]
Opcode::Extractlane- [x]
Opcode::ScalarToVector- [x]
Opcode::Splat- [x]
Opcode::VanyTrue- [x]
Opcode::VallTrue- [x]
Opcode::VhighBits- [x]
Opcode::Iconcat- [x]
Opcode::Isplit- [x]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSat- [x]
Opcode::Uunarrow</details>
aarch64
<details>
- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [x]
Opcode::Breduce- [x]
Opcode::Ireduce- [x]
Opcode::Bextend- [x]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [ ]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Extractlane- [x]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [ ]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote- [ ] Branches
</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
cfallin edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64 -- DONE!
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [x]
Opcode::Fcopysign- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Nearest- [x]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [x]
Opcode::Udiv- [x]
Opcode::Urem- [x]
Opcode::Sdiv- [x]
Opcode::Srem- [x]
Opcode::Umulhi- [x]
Opcode::Smulhi- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Insertlane- [x]
Opcode::Extractlane- [x]
Opcode::ScalarToVector- [x]
Opcode::Splat- [x]
Opcode::VanyTrue- [x]
Opcode::VallTrue- [x]
Opcode::VhighBits- [x]
Opcode::Iconcat- [x]
Opcode::Isplit- [x]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSat- [x]
Opcode::Uunarrow</details>
aarch64
<details>
- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [x]
Opcode::Breduce- [x]
Opcode::Ireduce- [x]
Opcode::Bextend- [x]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [ ]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Extractlane- [x]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [x]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote- [ ] Branches
</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
dheaton-arm commented on issue #3713:
I'm happy to do all of these tomorrow, unless someone else objects or has partial work here, then I can do the branch and flags-related ones (trueif/trueff, selectif/selectff/select, brif/brff/brz/brnz) once @dheaton-arm 's icmp/fcmp work is done.
@cfallin Just as a heads up, after my
icmppatch I've been working ontrue{if,ff}andselect{_,if,ff}. I haven't started on thebr*ops though. :)
dheaton-arm edited a comment on issue #3713:
I'm happy to do all of these tomorrow, unless someone else objects or has partial work here, then I can do the branch and flags-related ones (trueif/trueff, selectif/selectff/select, brif/brff/brz/brnz) once @dheaton-arm 's icmp/fcmp work is done.
@cfallin Just as a heads up, after my
icmppatch I've been working ontrue{if,ff}andselect{_,if*,ff}. I haven't started on thebr*ops though. :)
dheaton-arm edited a comment on issue #3713:
I'm happy to do all of these tomorrow, unless someone else objects or has partial work here, then I can do the branch and flags-related ones (trueif/trueff, selectif/selectff/select, brif/brff/brz/brnz) once @dheaton-arm 's icmp/fcmp work is done.
@cfallin Just as a heads up, after my
icmppatch I've been working ontrue{if,ff}andselect{_,if,if_spectreguard}. I haven't started on thebr*ops though. :)
cfallin commented on issue #3713:
@dheaton-arm great! I shifted over to some regalloc semantics cleanup work but I can come back and do
br*ops next, likely Thu or Fri, unless you want to claim then before then!
dheaton-arm commented on issue #3713:
@dheaton-arm great! I shifted over to some regalloc semantics cleanup work but I can come back and do
br*ops next, likely Thu or Fri, unless you want to claim then before then!I'm starting on the branch ops now, assuming you haven't yet. (Starting with
jumpandbr_icmp..brff.)
cfallin commented on issue #3713:
@dheaton-arm that sounds great; I didn't get to it last week as the regalloc stuff took longer than expected. Please feel free to grab all the branch ops and let me know if you need any help with any of the infra for that!
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64 -- DONE!
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [x]
Opcode::Fcopysign- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Nearest- [x]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [x]
Opcode::Udiv- [x]
Opcode::Urem- [x]
Opcode::Sdiv- [x]
Opcode::Srem- [x]
Opcode::Umulhi- [x]
Opcode::Smulhi- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Insertlane- [x]
Opcode::Extractlane- [x]
Opcode::ScalarToVector- [x]
Opcode::Splat- [x]
Opcode::VanyTrue- [x]
Opcode::VallTrue- [x]
Opcode::VhighBits- [x]
Opcode::Iconcat- [x]
Opcode::Isplit- [x]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSat- [x]
Opcode::Uunarrow</details>
aarch64
<details>
- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [x]
Opcode::Breduce- [x]
Opcode::Ireduce- [x]
Opcode::Bextend- [x]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Extractlane- [x]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [x]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote- [ ] Branches
</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
dheaton-arm commented on issue #3713:
The AArch64 backend has now been fully ported to ISLE.
fitzgen commented on issue #3713:
Unless I'm missing something, that means we can close this issue! Thanks so much to everyone who helped make this migration happen!
fitzgen closed issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64 -- DONE!
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [x]
Opcode::Fcopysign- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Nearest- [x]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [x]
Opcode::Udiv- [x]
Opcode::Urem- [x]
Opcode::Sdiv- [x]
Opcode::Srem- [x]
Opcode::Umulhi- [x]
Opcode::Smulhi- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Insertlane- [x]
Opcode::Extractlane- [x]
Opcode::ScalarToVector- [x]
Opcode::Splat- [x]
Opcode::VanyTrue- [x]
Opcode::VallTrue- [x]
Opcode::VhighBits- [x]
Opcode::Iconcat- [x]
Opcode::Isplit- [x]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSat- [x]
Opcode::Uunarrow</details>
aarch64
<details>
- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [x]
Opcode::Breduce- [x]
Opcode::Ireduce- [x]
Opcode::Bextend- [x]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Extractlane- [x]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [x]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote- [ ] Branches
</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
fitzgen edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64 -- DONE!
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [x]
Opcode::Fcopysign- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Nearest- [x]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [x]
Opcode::Udiv- [x]
Opcode::Urem- [x]
Opcode::Sdiv- [x]
Opcode::Srem- [x]
Opcode::Umulhi- [x]
Opcode::Smulhi- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Insertlane- [x]
Opcode::Extractlane- [x]
Opcode::ScalarToVector- [x]
Opcode::Splat- [x]
Opcode::VanyTrue- [x]
Opcode::VallTrue- [x]
Opcode::VhighBits- [x]
Opcode::Iconcat- [x]
Opcode::Isplit- [x]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSat- [x]
Opcode::Uunarrow</details>
aarch64 -- DONE!
<details>
- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [ ]
Opcode::Select- [ ]
Opcode::Selectif- [ ]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [ ]
Opcode::Trueif- [ ]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [x]
Opcode::Breduce- [x]
Opcode::Ireduce- [x]
Opcode::Bextend- [x]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [ ]
Opcode::Trapif- [ ]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Extractlane- [x]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [x]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote- [ ] Branches
</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
cfallin commented on issue #3713:
Thanks so much @dheaton-arm and other Arm folks (@akirilov-arm, @sparker-arm) for your contributions to this effort! It is great that we finally have everything in the DSL; this is going to enable us to make a bunch more improvements in the future, and really does help a lot.
akirilov-arm edited issue #3713:
This is a meta issue to track the migration from hand-written instruction selection and lowering over to using the ISLE DSL.
As you port lowering for a clif opcode over to ISLE, please check the associated box (or leave a comment, if you don't have edit permissions and I or someone else can check the box for you). Hopefully this will help us focus our porting efforts and finish the migration in a timely manner, as well as avoid stepping on each others toes by having two people accidentally port the same opcode lowerings.
cc @alexcrichton @cfallin @abrown @jlb6740 @uweigand @sparker-arm @akirilov-arm
x86_64 -- DONE!
<details>
- [x]
Opcode::Clz- [x]
Opcode::Ctz- [x]
Opcode::Popcnt- [x]
Opcode::Bitrev- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Uextend- [x]
Opcode::Sextend- [x]
Opcode::Breduce- [x]
Opcode::Bextend- [x]
Opcode::Ireduce- [x]
Opcode::Bint- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::Debugtrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fpromote- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fdemote- [x]
Opcode::Fvdemote- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddPairwise- [x]
Opcode::UwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::SwidenLow- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Bitcast- [x]
Opcode::Fabs- [x]
Opcode::Fneg- [x]
Opcode::Fcopysign- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Nearest- [x]
Opcode::Trunc- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::StackAddr- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [x]
Opcode::Udiv- [x]
Opcode::Urem- [x]
Opcode::Sdiv- [x]
Opcode::Srem- [x]
Opcode::Umulhi- [x]
Opcode::Smulhi- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Insertlane- [x]
Opcode::Extractlane- [x]
Opcode::ScalarToVector- [x]
Opcode::Splat- [x]
Opcode::VanyTrue- [x]
Opcode::VallTrue- [x]
Opcode::VhighBits- [x]
Opcode::Iconcat- [x]
Opcode::Isplit- [x]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSat- [x]
Opcode::Uunarrow</details>
aarch64 -- DONE!
<details>
- [x]
Opcode::Load- [x]
Opcode::Uload8- [x]
Opcode::Sload8- [x]
Opcode::Uload16- [x]
Opcode::Sload16- [x]
Opcode::Uload32- [x]
Opcode::Sload32- [x]
Opcode::Sload8x8- [x]
Opcode::Uload8x8- [x]
Opcode::Sload16x4- [x]
Opcode::Uload16x4- [x]
Opcode::Sload32x2- [x]
Opcode::Uload32x2- [x]
Opcode::Store- [x]
Opcode::Istore8- [x]
Opcode::Istore16- [x]
Opcode::Istore32- [x]
Opcode::StackAddr- [x]
Opcode::AtomicRmw- [x]
Opcode::AtomicCas- [x]
Opcode::AtomicLoad- [x]
Opcode::AtomicStore- [x]
Opcode::Fence- [x]
Opcode::Select- [x]
Opcode::Selectif- [x]
Opcode::SelectifSpectreGuard- [x]
Opcode::Bitselect- [x]
Opcode::Vselect- [x]
Opcode::Trueif- [x]
Opcode::Trueff- [x]
Opcode::IsNull- [x]
Opcode::IsInvalid- [x]
Opcode::Copy- [x]
Opcode::Breduce- [x]
Opcode::Ireduce- [x]
Opcode::Bextend- [x]
Opcode::Bmask- [x]
Opcode::Bint- [x]
Opcode::Bitcast- [x]
Opcode::FallthroughReturn- [x]
Opcode::Return- [x]
Opcode::Icmp- [x]
Opcode::Fcmp- [x]
Opcode::Debugtrap- [x]
Opcode::Trap- [x]
Opcode::ResumableTrap- [x]
Opcode::Trapif- [x]
Opcode::Trapff- [x]
Opcode::FuncAddr- [x]
Opcode::SymbolValue- [x]
Opcode::Call- [x]
Opcode::CallIndirect- [x]
Opcode::GetPinnedReg- [x]
Opcode::SetPinnedReg- [x]
Opcode::Vconst- [x]
Opcode::RawBitcast- [x]
Opcode::Extractlane- [x]
Opcode::Insertlane- [x]
Opcode::Splat- [x]
Opcode::ScalarToVector- [x]
Opcode::VallTrue- [x]
Opcode::VanyTrue- [x]
Opcode::VhighBits- [x]
Opcode::Shuffle- [x]
Opcode::Swizzle- [x]
Opcode::Isplit- [x]
Opcode::Iconcat- [x]
Opcode::Imax- [x]
Opcode::Umax- [x]
Opcode::Umin- [x]
Opcode::Imin- [x]
Opcode::IaddPairwise- [x]
Opcode::WideningPairwiseDotProductS- [x]
Opcode::Fadd- [x]
Opcode::Fsub- [x]
Opcode::Fmul- [x]
Opcode::Fdiv- [x]
Opcode::Fmin- [x]
Opcode::Fmax- [x]
Opcode::FminPseudo- [x]
Opcode::FmaxPseudo- [x]
Opcode::Sqrt- [x]
Opcode::Fneg- [x]
Opcode::Fabs- [x]
Opcode::Fpromote- [x]
Opcode::Fdemote- [x]
Opcode::Ceil- [x]
Opcode::Floor- [x]
Opcode::Trunc- [x]
Opcode::Nearest- [x]
Opcode::Fma- [x]
Opcode::Fcopysign- [x]
Opcode::FcvtToUint- [x]
Opcode::FcvtToSint- [x]
Opcode::FcvtFromUint- [x]
Opcode::FcvtFromSint- [x]
Opcode::FcvtToUintSat- [x]
Opcode::FcvtToSintSat- [x]
Opcode::IaddIfcout- [x]
Opcode::Iabs- [x]
Opcode::AvgRound- [x]
Opcode::Snarrow- [x]
Opcode::Unarrow- [x]
Opcode::Uunarrow- [x]
Opcode::SwidenLow- [x]
Opcode::SwidenHigh- [x]
Opcode::UwidenLow- [x]
Opcode::UwidenHigh- [x]
Opcode::TlsValue- [x]
Opcode::SqmulRoundSato- [x]
Opcode::FcvtLowFromSint- [x]
Opcode::FvpromoteLow- [x]
Opcode::Fvdemote- [x] Branches
</details>
s390x -- DONE!
<details>
- [x] Calls
- [x] Returns
- [x] Traps
- [x] Branches
</details>
Last updated: Dec 06 2025 at 06:05 UTC