fitzgen opened issue #3477:
Right now we manually do two
shl
s/shr
s and then compute the carry bits andor
them into the high half.We could just use
shld
andshrd
, which handle the carry bits for us.This is what LLVM does, fwiw: https://play.rust-lang.org/?version=stable&mode=release&edition=2021&gist=34e3a56cdaa9db7b1d5f4c429ad3db4f
fitzgen labeled issue #3477:
Right now we manually do two
shl
s/shr
s and then compute the carry bits andor
them into the high half.We could just use
shld
andshrd
, which handle the carry bits for us.This is what LLVM does, fwiw: https://play.rust-lang.org/?version=stable&mode=release&edition=2021&gist=34e3a56cdaa9db7b1d5f4c429ad3db4f
fitzgen labeled issue #3477:
Right now we manually do two
shl
s/shr
s and then compute the carry bits andor
them into the high half.We could just use
shld
andshrd
, which handle the carry bits for us.This is what LLVM does, fwiw: https://play.rust-lang.org/?version=stable&mode=release&edition=2021&gist=34e3a56cdaa9db7b1d5f4c429ad3db4f
cfallin commented on issue #3477:
Thanks for finding this inefficiency!
jlb6740 commented on issue #3477:
Hi @fitzgen Which lowering are you referring to? Can you point to the code sequence?
fitzgen commented on issue #3477:
@jlb6740 this sequence (and similar for
shr
):
cfallin labeled issue #3477:
Right now we manually do two
shl
s/shr
s and then compute the carry bits andor
them into the high half.We could just use
shld
andshrd
, which handle the carry bits for us.This is what LLVM does, fwiw: https://play.rust-lang.org/?version=stable&mode=release&edition=2021&gist=34e3a56cdaa9db7b1d5f4c429ad3db4f
Last updated: Dec 23 2024 at 12:05 UTC