bjorn3 opened issue #3064:
Steps to Reproduce
Try to compile an ishl instruction with an i128 rhs using the AArch64 backend.
Expected Results
It compiles
Actual Results
thread 'rustc' panicked at 'Multi-register value not expected', /home/runner/.cargo/git/checkouts/wasmtime-41807828cb3a7a7e/c71ad94/cranelift/codegen/src/isa/aarch64/lower.rs:297:10 stack backtrace: [...] 2: core::option::expect_failed at /rustc/6d820866a27b1949e237be79b9c8c0145fe728b7/library/core/src/option.rs:1243:5 3: cranelift_codegen::isa::aarch64::lower_inst::lower_insn_to_regs 4: cranelift_codegen::machinst::lower::Lower<I>::lower 5: cranelift_codegen::machinst::compile::compile 6: <cranelift_codegen::isa::aarch64::AArch64Backend as cranelift_codegen::machinst::MachBackend>::compile_function
Versions and Environment
Cranelift version or commit: c71ad9490e7f3e19bbcae7e28bbe50f8a0b4a5d8
Operating system: N/A
Architecture: AArch64
Extra Info
AArch64 counterpart to https://github.com/bytecodealliance/wasmtime/issues/2727
bjorn3 labeled issue #3064:
Steps to Reproduce
Try to compile an ishl instruction with an i128 rhs using the AArch64 backend.
Expected Results
It compiles
Actual Results
thread 'rustc' panicked at 'Multi-register value not expected', /home/runner/.cargo/git/checkouts/wasmtime-41807828cb3a7a7e/c71ad94/cranelift/codegen/src/isa/aarch64/lower.rs:297:10 stack backtrace: [...] 2: core::option::expect_failed at /rustc/6d820866a27b1949e237be79b9c8c0145fe728b7/library/core/src/option.rs:1243:5 3: cranelift_codegen::isa::aarch64::lower_inst::lower_insn_to_regs 4: cranelift_codegen::machinst::lower::Lower<I>::lower 5: cranelift_codegen::machinst::compile::compile 6: <cranelift_codegen::isa::aarch64::AArch64Backend as cranelift_codegen::machinst::MachBackend>::compile_function
Versions and Environment
Cranelift version or commit: c71ad9490e7f3e19bbcae7e28bbe50f8a0b4a5d8
Operating system: N/A
Architecture: AArch64
Extra Info
AArch64 counterpart to https://github.com/bytecodealliance/wasmtime/issues/2727
bjorn3 labeled issue #3064:
Steps to Reproduce
Try to compile an ishl instruction with an i128 rhs using the AArch64 backend.
Expected Results
It compiles
Actual Results
thread 'rustc' panicked at 'Multi-register value not expected', /home/runner/.cargo/git/checkouts/wasmtime-41807828cb3a7a7e/c71ad94/cranelift/codegen/src/isa/aarch64/lower.rs:297:10 stack backtrace: [...] 2: core::option::expect_failed at /rustc/6d820866a27b1949e237be79b9c8c0145fe728b7/library/core/src/option.rs:1243:5 3: cranelift_codegen::isa::aarch64::lower_inst::lower_insn_to_regs 4: cranelift_codegen::machinst::lower::Lower<I>::lower 5: cranelift_codegen::machinst::compile::compile 6: <cranelift_codegen::isa::aarch64::AArch64Backend as cranelift_codegen::machinst::MachBackend>::compile_function
Versions and Environment
Cranelift version or commit: c71ad9490e7f3e19bbcae7e28bbe50f8a0b4a5d8
Operating system: N/A
Architecture: AArch64
Extra Info
AArch64 counterpart to https://github.com/bytecodealliance/wasmtime/issues/2727
bjorn3 commented on issue #3064:
Found by https://github.com/bjorn3/rustc_codegen_cranelift/commit/11584b52966cc71bdae39ac1733ea929201c517f.
cfallin commented on issue #3064:
cc @afonso360
afonso360 commented on issue #3064:
This is interesting, because we have tests for this! https://github.com/bytecodealliance/wasmtime/blob/c71ad9490e7f3e19bbcae7e28bbe50f8a0b4a5d8/cranelift/filetests/filetests/runtests/i128-arithmetic.clif#L98
I need to look into this a bit more
bjorn3 commented on issue #3064:
The lhs is i8 in this case. Maybe it only gets handled when the lhs and rhs are both i128?
afonso360 commented on issue #3064:
I think they are both i128, lhs is obtained from
iconcat v0, v1
, and rhs isiconcat v4, v4
.
bjorn3 commented on issue #3064:
I mean in case of the bug the lhs is i8.
afonso360 commented on issue #3064:
Oh, right, we also have test for those: https://github.com/bytecodealliance/wasmtime/blob/c71ad9490e7f3e19bbcae7e28bbe50f8a0b4a5d8/cranelift/filetests/filetests/runtests/i128-arithmetic.clif#L76
Are you able to get a clif file from cg_clif?
bjorn3 commented on issue #3064:
That test is the opposite way around. There the lhs is i128 and the rhs is i8. In my case the lhs is i8 and the rhs is i128. I don't have a clif file at hand, but I would guess it did be:
function %ishl_i128_i8(i64, i64, i8) -> i8 { block0(v0: i64, v1: i64, v2: i8): v3 = iconcat v0, v1 v4 = ishl.i8 v2, v3 return v4 }
afonso360 commented on issue #3064:
Oh, sorry, got it!
Yeah i'll have a look
akirilov-arm closed issue #3064:
Steps to Reproduce
Try to compile an ishl instruction with an i128 rhs using the AArch64 backend.
Expected Results
It compiles
Actual Results
thread 'rustc' panicked at 'Multi-register value not expected', /home/runner/.cargo/git/checkouts/wasmtime-41807828cb3a7a7e/c71ad94/cranelift/codegen/src/isa/aarch64/lower.rs:297:10 stack backtrace: [...] 2: core::option::expect_failed at /rustc/6d820866a27b1949e237be79b9c8c0145fe728b7/library/core/src/option.rs:1243:5 3: cranelift_codegen::isa::aarch64::lower_inst::lower_insn_to_regs 4: cranelift_codegen::machinst::lower::Lower<I>::lower 5: cranelift_codegen::machinst::compile::compile 6: <cranelift_codegen::isa::aarch64::AArch64Backend as cranelift_codegen::machinst::MachBackend>::compile_function
Versions and Environment
Cranelift version or commit: c71ad9490e7f3e19bbcae7e28bbe50f8a0b4a5d8
Operating system: N/A
Architecture: AArch64
Extra Info
AArch64 counterpart to https://github.com/bytecodealliance/wasmtime/issues/2727
Last updated: Dec 23 2024 at 12:05 UTC