Stream: git-wasmtime

Topic: wasmtime / issue #2716 [x64] Coalesce loads/stores when p...

view this post on Zulip Wasmtime GitHub notifications bot (Sep 01 2022 at 01:11):

jameysharp commented on issue #2716:

Now that the x64 backend is migrated to ISLE, is it time to re-visit this optimization? cc: @elliottt

view this post on Zulip Wasmtime GitHub notifications bot (Sep 01 2022 at 07:31):

bjorn3 commented on issue #2716:

This is only allowed for aligned pointers, right? Can you check the aligned memflag?

view this post on Zulip Wasmtime GitHub notifications bot (Feb 09 2023 at 00:28):

cfallin commented on issue #2716:

@abrown are you interested in pursuing this further? (Going through old PRs and cleaning up...) I agree with @bjorn3 that the alignment issue is the critical question here, and so I suspect there won't be major opportunity coming from Wasm-SIMD (given that loads/stores only have alignment hints, not hard-enforced requirements), but we can still think about it further if there's some other aspect where it could help...

view this post on Zulip Wasmtime GitHub notifications bot (Feb 10 2023 at 18:49):

abrown commented on issue #2716:

I had to refresh my mental cache for this issue quite a bit (it's been a while for this issue!). I don't know why I didn't originally respond, but as I dug into this, I didn't immediately find any requirement for these instructions to use aligned addresses. [searches more...] In fact, I do see the following in section 12.10.7 of the Intel manuals:

view this post on Zulip Wasmtime GitHub notifications bot (Feb 10 2023 at 18:50):

abrown edited a comment on issue #2716:

I had to refresh my mental cache for this issue quite a bit (it's been a while for this issue!). I don't know why I didn't originally respond, but as I dug into this, I didn't immediately find any requirement for these instructions to use aligned addresses. [searches more...] In fact, I do see the following in section 12.10.7 of the Intel manuals:

SSE4.1 adds 7 instructions (corresponding to 9 assembly instruction mnemonics) that simplify data insertion and extraction between general-purpose register (GPR) and XMM registers (EXTRACTPS, INSERTPS, PINSRB, PINSRD, PINSRQ, PEXTRB, PEXTRW, PEXTRD, and PEXTRQ). When accessing memory, no alignment is required for any of these instructions (unless alignment checking is enabled).

I think we could proceed with adding these tests?

Last updated: Oct 23 2024 at 20:03 UTC