jlb6740 commented on issue #2272:
Instructions added after this table was initially put together include:
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-- | -- | --
f32x4.demote_f64x2_zero | 0x5e |
f64x2.convert_low_i32x4_s | 0xfe |
f64x2.convert_low_i32x4_u | 0xff |
f64x2.promote_low_f32x4 | 0x5f |
i16x8.extadd_pairwise_i8x16_s | 0x7c |
i16x8.extadd_pairwise_i8x16_u | 0x7d |
i16x8.extend_high_i8x16_s | 0x88 |
i16x8.extend_high_i8x16_u | 0x8a |
i16x8.extend_low_i8x16_s | 0x87 |
i16x8.extend_low_i8x16_u | 0x89 |
i16x8.extmul_high_i8x16_s | 0x9d |
i16x8.extmul_high_i8x16_u | 0x9f |
i16x8.extmul_low_i8x16_s | 0x9c |
i16x8.extmul_low_i8x16_u | 0x9e |
i16x8.q15mulr_sat_s | 0x82 |
i32x4.extadd_pairwise_i16x8_s | 0x7e |
i32x4.extadd_pairwise_i16x8_u | 0x7f |
i32x4.extend_high_i16x8_s | 0xa8 |
i32x4.extend_high_i16x8_u | 0xaa |
i32x4.extend_low_i16x8_s | 0xa7 |
i32x4.extend_low_i16x8_u | 0xa9 |
i32x4.extmul_high_i16x8_s | 0xbd |
i32x4.extmul_high_i16x8_u | 0xbf |
i32x4.extmul_low_i16x8_s | 0xbc |
i32x4.extmul_low_i16x8_u | 0xbe |
i32x4.trunc_sat_f64x2_s_zero | 0xfc |
i32x4.trunc_sat_f64x2_u_zero | 0xfd |
i64x2.abs | 0xc0 |
i64x2.all_true | 0xc3 |
i64x2.eq | 0xd6 |
i64x2.extend_high_i32x4_s | 0xc8 |
i64x2.extend_high_i32x4_u | 0xca |
i64x2.extend_low_i32x4_s | 0xc7 |
i64x2.extend_low_i32x4_u | 0xc9 |
i64x2.extmul_high_i32x4_s | 0xdd |
i64x2.extmul_high_i32x4_u | 0xdf |
i64x2.extmul_low_i32x4_s | 0xdc |
i64x2.extmul_low_i32x4_u | 0xde |
i64x2.ge_s | 0xdb |
i64x2.gt_s | 0xd9 |
i64x2.le_s | 0xda |
i64x2.lt_s | 0xd8 |
i64x2.ne | 0xd7 |
v128.any_true | 0x53 |
v128.load16_lane | 0x55 |
v128.load32_lane | 0x56 |
v128.load64_lane | 0x57 |
v128.load8_lane | 0x54 |
v128.store16_lane | 0x59 |
v128.store32_lane | 0x5a |
v128.store64_lane | 0x5b |
v128.store8_lane | 0x58 |
jlb6740 edited a comment on issue #2272:
Instructions added after this table was initially put together include:
Name |
Opcode |
Status |
f32x4.demote_f64x2_zero |
0x5e |
|
f64x2.convert_low_i32x4_s |
0xfe |
|
f64x2.convert_low_i32x4_u |
0xff |
|
f64x2.promote_low_f32x4 |
0x5f |
|
i16x8.extadd_pairwise_i8x16_s |
0x7c |
|
i16x8.extadd_pairwise_i8x16_u |
0x7d |
|
i16x8.extend_high_i8x16_s |
0x88 |
|
i16x8.extend_high_i8x16_u |
0x8a |
|
i16x8.extend_low_i8x16_s |
0x87 |
|
i16x8.extend_low_i8x16_u |
0x89 |
|
i16x8.extmul_high_i8x16_s |
0x9d |
|
i16x8.extmul_high_i8x16_u |
0x9f |
|
i16x8.extmul_low_i8x16_s |
0x9c |
|
i16x8.extmul_low_i8x16_u |
0x9e |
|
i16x8.q15mulr_sat_s |
0x82 |
|
i32x4.extadd_pairwise_i16x8_s |
0x7e |
|
i32x4.extadd_pairwise_i16x8_u |
0x7f |
|
i32x4.extend_high_i16x8_s |
0xa8 |
|
i32x4.extend_high_i16x8_u |
0xaa |
|
i32x4.extend_low_i16x8_s |
0xa7 |
|
i32x4.extend_low_i16x8_u |
0xa9 |
|
i32x4.extmul_high_i16x8_s |
0xbd |
|
i32x4.extmul_high_i16x8_u |
0xbf |
|
i32x4.extmul_low_i16x8_s |
0xbc |
|
i32x4.extmul_low_i16x8_u |
0xbe |
|
i32x4.trunc_sat_f64x2_s_zero |
0xfc |
|
i32x4.trunc_sat_f64x2_u_zero |
0xfd |
|
i64x2.abs |
0xc0 |
|
i64x2.all_true |
0xc3 |
|
i64x2.eq |
0xd6 |
|
i64x2.extend_high_i32x4_s |
0xc8 |
|
i64x2.extend_high_i32x4_u |
0xca |
|
i64x2.extend_low_i32x4_s |
0xc7 |
|
i64x2.extend_low_i32x4_u |
0xc9 |
|
i64x2.extmul_high_i32x4_s |
0xdd |
|
i64x2.extmul_high_i32x4_u |
0xdf |
|
i64x2.extmul_low_i32x4_s |
0xdc |
|
i64x2.extmul_low_i32x4_u |
0xde |
|
i64x2.ge_s |
0xdb |
|
i64x2.gt_s |
0xd9 |
|
i64x2.le_s |
0xda |
|
i64x2.lt_s |
0xd8 |
|
i64x2.ne |
0xd7 |
|
v128.any_true |
0x53 |
|
v128.load16_lane |
0x55 |
|
v128.load32_lane |
0x56 |
|
v128.load64_lane |
0x57 |
|
v128.load8_lane |
0x54 |
|
v128.store16_lane |
0x59 |
|
v128.store32_lane |
0x5a |
|
v128.store64_lane |
0x5b |
|
v128.store8_lane |
0x58 |
|
|
|
|
jlb6740 edited a comment on issue #2272:
Instructions added to the spec after table above was put together include:
Name |
Opcode |
Status |
f32x4.demote_f64x2_zero |
0x5e |
|
f64x2.convert_low_i32x4_s |
0xfe |
|
f64x2.convert_low_i32x4_u |
0xff |
|
f64x2.promote_low_f32x4 |
0x5f |
|
i16x8.extadd_pairwise_i8x16_s |
0x7c |
|
i16x8.extadd_pairwise_i8x16_u |
0x7d |
|
i16x8.extend_high_i8x16_s |
0x88 |
|
i16x8.extend_high_i8x16_u |
0x8a |
|
i16x8.extend_low_i8x16_s |
0x87 |
|
i16x8.extend_low_i8x16_u |
0x89 |
|
i16x8.extmul_high_i8x16_s |
0x9d |
|
i16x8.extmul_high_i8x16_u |
0x9f |
|
i16x8.extmul_low_i8x16_s |
0x9c |
|
i16x8.extmul_low_i8x16_u |
0x9e |
|
i16x8.q15mulr_sat_s |
0x82 |
|
i32x4.extadd_pairwise_i16x8_s |
0x7e |
|
i32x4.extadd_pairwise_i16x8_u |
0x7f |
|
i32x4.extend_high_i16x8_s |
0xa8 |
|
i32x4.extend_high_i16x8_u |
0xaa |
|
i32x4.extend_low_i16x8_s |
0xa7 |
|
i32x4.extend_low_i16x8_u |
0xa9 |
|
i32x4.extmul_high_i16x8_s |
0xbd |
|
i32x4.extmul_high_i16x8_u |
0xbf |
|
i32x4.extmul_low_i16x8_s |
0xbc |
|
i32x4.extmul_low_i16x8_u |
0xbe |
|
i32x4.trunc_sat_f64x2_s_zero |
0xfc |
|
i32x4.trunc_sat_f64x2_u_zero |
0xfd |
|
i64x2.abs |
0xc0 |
|
i64x2.all_true |
0xc3 |
|
i64x2.eq |
0xd6 |
|
i64x2.extend_high_i32x4_s |
0xc8 |
|
i64x2.extend_high_i32x4_u |
0xca |
|
i64x2.extend_low_i32x4_s |
0xc7 |
|
i64x2.extend_low_i32x4_u |
0xc9 |
|
i64x2.extmul_high_i32x4_s |
0xdd |
|
i64x2.extmul_high_i32x4_u |
0xdf |
|
i64x2.extmul_low_i32x4_s |
0xdc |
|
i64x2.extmul_low_i32x4_u |
0xde |
|
i64x2.ge_s |
0xdb |
|
i64x2.gt_s |
0xd9 |
|
i64x2.le_s |
0xda |
|
i64x2.lt_s |
0xd8 |
|
i64x2.ne |
0xd7 |
|
v128.any_true |
0x53 |
|
v128.load16_lane |
0x55 |
|
v128.load32_lane |
0x56 |
|
v128.load64_lane |
0x57 |
|
v128.load8_lane |
0x54 |
|
v128.store16_lane |
0x59 |
|
v128.store32_lane |
0x5a |
|
v128.store64_lane |
0x5b |
|
v128.store8_lane |
0x58 |
|
|
|
|
jlb6740 closed issue #2272:
Last Update: 1/14/2021
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load32_zero |
0xfc |
-- |
:+1: |
v128.load64_zero |
0xfd |
-- |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
:+1: |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
:+1: |
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
:+1: |
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
:+1: |
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
:+1: |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
------------ |
0x74 |
-- |
-- |
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
------------ |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
:+1: |
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
:+1: |
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
:+1: |
i16x8.shl |
0x8b |
:+1: |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
:+1: |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
------------ |
0x94 |
-- |
-- |
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
----------- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
:+1: |
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
:+1: |
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
:+1: |
i32x4.shl |
0xab |
:+1: |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
:+1: |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
i32x4.dot_i16x8_s |
0xba |
-- |
@abrown |
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
:+1: |
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
i64x2.bitmask |
0xc4 |
-- |
? |
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
i64x2.widen_low_i32x4_s |
0xc7 |
-- |
? |
i64x2.widen_high_i32x4_s |
0xc8 |
-- |
? |
i64x2.widen_low_i32x4_u |
0xc9 |
-- |
? |
i64x2.widen_high_i32x4_u |
0xca |
-- |
? |
i64x2.shl |
0xcb |
:+1: |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
:+1: |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
:+1: |
f32x4.floor |
0xd9 |
:question: |
:+1: |
f32x4.trunc |
0xda |
:question: |
:+1: |
f32x4.nearest |
0xdb |
:question: |
:+1: |
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
:+1: |
f32x4.pmax |
0xeb |
:question: |
:+1: |
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
:+1: |
f64x2.floor |
0xdd |
:question: |
:+1: |
f64x2.trunc |
0xde |
:question: |
:+1: |
f64x2.nearest |
0xdf |
:question: |
:+1: |
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
:+1: |
f64x2.pmax |
0xf7 |
:question: |
:+1: |
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:question: |
:+1: |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:question: |
:+1: |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
:+1: |
f32x4.convert_i32x4_u |
0xfb |
:question: |
:+1: |
jlb6740 reopened issue #2272:
Last Update: 1/14/2021
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load32_zero |
0xfc |
-- |
:+1: |
v128.load64_zero |
0xfd |
-- |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
:+1: |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
:+1: |
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
:+1: |
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
:+1: |
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
:+1: |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
------------ |
0x74 |
-- |
-- |
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
------------ |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
:+1: |
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
:+1: |
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
:+1: |
i16x8.shl |
0x8b |
:+1: |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
:+1: |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
------------ |
0x94 |
-- |
-- |
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
----------- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
:+1: |
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
:+1: |
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
:+1: |
i32x4.shl |
0xab |
:+1: |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
:+1: |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
i32x4.dot_i16x8_s |
0xba |
-- |
@abrown |
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
:+1: |
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
i64x2.bitmask |
0xc4 |
-- |
? |
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
i64x2.widen_low_i32x4_s |
0xc7 |
-- |
? |
i64x2.widen_high_i32x4_s |
0xc8 |
-- |
? |
i64x2.widen_low_i32x4_u |
0xc9 |
-- |
? |
i64x2.widen_high_i32x4_u |
0xca |
-- |
? |
i64x2.shl |
0xcb |
:+1: |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
:+1: |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
:+1: |
f32x4.floor |
0xd9 |
:question: |
:+1: |
f32x4.trunc |
0xda |
:question: |
:+1: |
f32x4.nearest |
0xdb |
:question: |
:+1: |
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
:+1: |
f32x4.pmax |
0xeb |
:question: |
:+1: |
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
:+1: |
f64x2.floor |
0xdd |
:question: |
:+1: |
f64x2.trunc |
0xde |
:question: |
:+1: |
f64x2.nearest |
0xdf |
:question: |
:+1: |
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
:+1: |
f64x2.pmax |
0xf7 |
:question: |
:+1: |
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:question: |
:+1: |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:question: |
:+1: |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
:+1: |
f32x4.convert_i32x4_u |
0xfb |
:question: |
:+1: |
jlb6740 edited a comment on issue #2272:
Instructions added to the spec after table above was put together include:
Name |
Opcode |
Status |
f32x4.demote_f64x2_zero |
0x5e |
|
f64x2.convert_low_i32x4_s |
0xfe |
|
f64x2.convert_low_i32x4_u |
0xff |
|
f64x2.promote_low_f32x4 |
0x5f |
|
i16x8.extadd_pairwise_i8x16_s |
0x7c |
|
i16x8.extadd_pairwise_i8x16_u |
0x7d |
|
i16x8.extend_high_i8x16_s |
0x88 |
|
i16x8.extend_high_i8x16_u |
0x8a |
|
i16x8.extend_low_i8x16_s |
0x87 |
|
i16x8.extend_low_i8x16_u |
0x89 |
|
i16x8.extmul_high_i8x16_s |
0x9d |
|
i16x8.extmul_high_i8x16_u |
0x9f |
|
i16x8.extmul_low_i8x16_s |
0x9c |
|
i16x8.extmul_low_i8x16_u |
0x9e |
|
i16x8.q15mulr_sat_s |
0x82 |
|
i32x4.extadd_pairwise_i16x8_s |
0x7e |
|
i32x4.extadd_pairwise_i16x8_u |
0x7f |
|
i32x4.extend_high_i16x8_s |
0xa8 |
|
i32x4.extend_high_i16x8_u |
0xaa |
|
i32x4.extend_low_i16x8_s |
0xa7 |
|
i32x4.extend_low_i16x8_u |
0xa9 |
|
i32x4.extmul_high_i16x8_s |
0xbd |
|
i32x4.extmul_high_i16x8_u |
0xbf |
|
i32x4.extmul_low_i16x8_s |
0xbc |
|
i32x4.extmul_low_i16x8_u |
0xbe |
|
i32x4.trunc_sat_f64x2_s_zero |
0xfc |
|
i32x4.trunc_sat_f64x2_u_zero |
0xfd |
|
i64x2.abs |
0xc0 |
|
i64x2.all_true |
0xc3 |
|
i64x2.eq |
0xd6 |
|
i64x2.extend_high_i32x4_s |
0xc8 |
|
i64x2.extend_high_i32x4_u |
0xca |
|
i64x2.extend_low_i32x4_s |
0xc7 |
|
i64x2.extend_low_i32x4_u |
0xc9 |
|
i64x2.extmul_high_i32x4_s |
0xdd |
|
i64x2.extmul_high_i32x4_u |
0xdf |
|
i64x2.extmul_low_i32x4_s |
0xdc |
:+1: |
i64x2.extmul_low_i32x4_u |
0xde |
|
i64x2.ge_s |
0xdb |
|
i64x2.gt_s |
0xd9 |
|
i64x2.le_s |
0xda |
|
i64x2.lt_s |
0xd8 |
|
i64x2.ne |
0xd7 |
|
v128.any_true |
0x53 |
|
v128.load16_lane |
0x55 |
|
v128.load32_lane |
0x56 |
|
v128.load64_lane |
0x57 |
|
v128.load8_lane |
0x54 |
|
v128.store16_lane |
0x59 |
|
v128.store32_lane |
0x5a |
|
v128.store64_lane |
0x5b |
|
v128.store8_lane |
0x58 |
|
|
|
|
jlb6740 edited a comment on issue #2272:
Instructions added to the spec after table above was put together include:
Name |
Opcode |
Status |
f32x4.demote_f64x2_zero |
0x5e |
:+1: |
f64x2.convert_low_i32x4_s |
0xfe |
|
f64x2.convert_low_i32x4_u |
0xff |
|
f64x2.promote_low_f32x4 |
0x5f |
|
i16x8.extadd_pairwise_i8x16_s |
0x7c |
|
i16x8.extadd_pairwise_i8x16_u |
0x7d |
|
i16x8.extend_high_i8x16_s |
0x88 |
|
i16x8.extend_high_i8x16_u |
0x8a |
|
i16x8.extend_low_i8x16_s |
0x87 |
|
i16x8.extend_low_i8x16_u |
0x89 |
|
i16x8.extmul_high_i8x16_s |
0x9d |
|
i16x8.extmul_high_i8x16_u |
0x9f |
|
i16x8.extmul_low_i8x16_s |
0x9c |
|
i16x8.extmul_low_i8x16_u |
0x9e |
|
i16x8.q15mulr_sat_s |
0x82 |
|
i32x4.extadd_pairwise_i16x8_s |
0x7e |
|
i32x4.extadd_pairwise_i16x8_u |
0x7f |
|
i32x4.extend_high_i16x8_s |
0xa8 |
|
i32x4.extend_high_i16x8_u |
0xaa |
|
i32x4.extend_low_i16x8_s |
0xa7 |
|
i32x4.extend_low_i16x8_u |
0xa9 |
|
i32x4.extmul_high_i16x8_s |
0xbd |
|
i32x4.extmul_high_i16x8_u |
0xbf |
|
i32x4.extmul_low_i16x8_s |
0xbc |
|
i32x4.extmul_low_i16x8_u |
0xbe |
|
i32x4.trunc_sat_f64x2_s_zero |
0xfc |
|
i32x4.trunc_sat_f64x2_u_zero |
0xfd |
|
i64x2.abs |
0xc0 |
|
i64x2.all_true |
0xc3 |
|
i64x2.eq |
0xd6 |
|
i64x2.extend_high_i32x4_s |
0xc8 |
|
i64x2.extend_high_i32x4_u |
0xca |
|
i64x2.extend_low_i32x4_s |
0xc7 |
|
i64x2.extend_low_i32x4_u |
0xc9 |
|
i64x2.extmul_high_i32x4_s |
0xdd |
|
i64x2.extmul_high_i32x4_u |
0xdf |
|
i64x2.extmul_low_i32x4_s |
0xdc |
|
i64x2.extmul_low_i32x4_u |
0xde |
|
i64x2.ge_s |
0xdb |
|
i64x2.gt_s |
0xd9 |
|
i64x2.le_s |
0xda |
|
i64x2.lt_s |
0xd8 |
|
i64x2.ne |
0xd7 |
|
v128.any_true |
0x53 |
|
v128.load16_lane |
0x55 |
|
v128.load32_lane |
0x56 |
|
v128.load64_lane |
0x57 |
|
v128.load8_lane |
0x54 |
|
v128.store16_lane |
0x59 |
|
v128.store32_lane |
0x5a |
|
v128.store64_lane |
0x5b |
|
v128.store8_lane |
0x58 |
|
|
|
|
jlb6740 edited a comment on issue #2272:
Instructions added to the spec after table above was put together include:
Name |
Opcode |
Status |
f32x4.demote_f64x2_zero |
0x5e |
:+1: |
f64x2.convert_low_i32x4_s |
0xfe |
|
f64x2.convert_low_i32x4_u |
0xff |
|
f64x2.promote_low_f32x4 |
0x5f |
:+1: |
i16x8.extadd_pairwise_i8x16_s |
0x7c |
|
i16x8.extadd_pairwise_i8x16_u |
0x7d |
|
i16x8.extend_high_i8x16_s |
0x88 |
|
i16x8.extend_high_i8x16_u |
0x8a |
|
i16x8.extend_low_i8x16_s |
0x87 |
|
i16x8.extend_low_i8x16_u |
0x89 |
|
i16x8.extmul_high_i8x16_s |
0x9d |
|
i16x8.extmul_high_i8x16_u |
0x9f |
|
i16x8.extmul_low_i8x16_s |
0x9c |
|
i16x8.extmul_low_i8x16_u |
0x9e |
|
i16x8.q15mulr_sat_s |
0x82 |
|
i32x4.extadd_pairwise_i16x8_s |
0x7e |
|
i32x4.extadd_pairwise_i16x8_u |
0x7f |
|
i32x4.extend_high_i16x8_s |
0xa8 |
|
i32x4.extend_high_i16x8_u |
0xaa |
|
i32x4.extend_low_i16x8_s |
0xa7 |
|
i32x4.extend_low_i16x8_u |
0xa9 |
|
i32x4.extmul_high_i16x8_s |
0xbd |
|
i32x4.extmul_high_i16x8_u |
0xbf |
|
i32x4.extmul_low_i16x8_s |
0xbc |
|
i32x4.extmul_low_i16x8_u |
0xbe |
|
i32x4.trunc_sat_f64x2_s_zero |
0xfc |
|
i32x4.trunc_sat_f64x2_u_zero |
0xfd |
|
i64x2.abs |
0xc0 |
|
i64x2.all_true |
0xc3 |
|
i64x2.eq |
0xd6 |
|
i64x2.extend_high_i32x4_s |
0xc8 |
|
i64x2.extend_high_i32x4_u |
0xca |
|
i64x2.extend_low_i32x4_s |
0xc7 |
|
i64x2.extend_low_i32x4_u |
0xc9 |
|
i64x2.extmul_high_i32x4_s |
0xdd |
|
i64x2.extmul_high_i32x4_u |
0xdf |
|
i64x2.extmul_low_i32x4_s |
0xdc |
|
i64x2.extmul_low_i32x4_u |
0xde |
|
i64x2.ge_s |
0xdb |
|
i64x2.gt_s |
0xd9 |
|
i64x2.le_s |
0xda |
|
i64x2.lt_s |
0xd8 |
|
i64x2.ne |
0xd7 |
|
v128.any_true |
0x53 |
|
v128.load16_lane |
0x55 |
|
v128.load32_lane |
0x56 |
|
v128.load64_lane |
0x57 |
|
v128.load8_lane |
0x54 |
|
v128.store16_lane |
0x59 |
|
v128.store32_lane |
0x5a |
|
v128.store64_lane |
0x5b |
|
v128.store8_lane |
0x58 |
|
|
|
|
jlb6740 edited a comment on issue #2272:
Instructions added to the spec after table above was put together include:
Name |
Opcode |
Status |
f32x4.demote_f64x2_zero |
0x5e |
:+1: |
f64x2.convert_low_i32x4_s |
0xfe |
:+1: |
f64x2.convert_low_i32x4_u |
0xff |
|
f64x2.promote_low_f32x4 |
0x5f |
:+1: |
i16x8.extadd_pairwise_i8x16_s |
0x7c |
|
i16x8.extadd_pairwise_i8x16_u |
0x7d |
|
i16x8.extend_high_i8x16_s |
0x88 |
|
i16x8.extend_high_i8x16_u |
0x8a |
|
i16x8.extend_low_i8x16_s |
0x87 |
|
i16x8.extend_low_i8x16_u |
0x89 |
|
i16x8.extmul_high_i8x16_s |
0x9d |
|
i16x8.extmul_high_i8x16_u |
0x9f |
|
i16x8.extmul_low_i8x16_s |
0x9c |
|
i16x8.extmul_low_i8x16_u |
0x9e |
|
i16x8.q15mulr_sat_s |
0x82 |
|
i32x4.extadd_pairwise_i16x8_s |
0x7e |
|
i32x4.extadd_pairwise_i16x8_u |
0x7f |
|
i32x4.extend_high_i16x8_s |
0xa8 |
|
i32x4.extend_high_i16x8_u |
0xaa |
|
i32x4.extend_low_i16x8_s |
0xa7 |
|
i32x4.extend_low_i16x8_u |
0xa9 |
|
i32x4.extmul_high_i16x8_s |
0xbd |
|
i32x4.extmul_high_i16x8_u |
0xbf |
|
i32x4.extmul_low_i16x8_s |
0xbc |
|
i32x4.extmul_low_i16x8_u |
0xbe |
|
i32x4.trunc_sat_f64x2_s_zero |
0xfc |
|
i32x4.trunc_sat_f64x2_u_zero |
0xfd |
|
i64x2.abs |
0xc0 |
|
i64x2.all_true |
0xc3 |
|
i64x2.eq |
0xd6 |
|
i64x2.extend_high_i32x4_s |
0xc8 |
|
i64x2.extend_high_i32x4_u |
0xca |
|
i64x2.extend_low_i32x4_s |
0xc7 |
|
i64x2.extend_low_i32x4_u |
0xc9 |
|
i64x2.extmul_high_i32x4_s |
0xdd |
|
i64x2.extmul_high_i32x4_u |
0xdf |
|
i64x2.extmul_low_i32x4_s |
0xdc |
|
i64x2.extmul_low_i32x4_u |
0xde |
|
i64x2.ge_s |
0xdb |
|
i64x2.gt_s |
0xd9 |
|
i64x2.le_s |
0xda |
|
i64x2.lt_s |
0xd8 |
|
i64x2.ne |
0xd7 |
|
v128.any_true |
0x53 |
|
v128.load16_lane |
0x55 |
|
v128.load32_lane |
0x56 |
|
v128.load64_lane |
0x57 |
|
v128.load8_lane |
0x54 |
|
v128.store16_lane |
0x59 |
|
v128.store32_lane |
0x5a |
|
v128.store64_lane |
0x5b |
|
v128.store8_lane |
0x58 |
|
|
|
|
jlb6740 edited a comment on issue #2272:
Instructions added to the spec after table above was put together include:
Name |
Opcode |
Status |
f32x4.demote_f64x2_zero |
0x5e |
:+1: |
f64x2.convert_low_i32x4_s |
0xfe |
:+1: |
f64x2.convert_low_i32x4_u |
0xff |
#2982 |
f64x2.promote_low_f32x4 |
0x5f |
:+1: |
i16x8.extadd_pairwise_i8x16_s |
0x7c |
InProgress |
i16x8.extadd_pairwise_i8x16_u |
0x7d |
InProgress |
i16x8.extend_high_i8x16_s |
0x88 |
|
i16x8.extend_high_i8x16_u |
0x8a |
|
i16x8.extend_low_i8x16_s |
0x87 |
|
i16x8.extend_low_i8x16_u |
0x89 |
|
i16x8.extmul_high_i8x16_s |
0x9d |
|
i16x8.extmul_high_i8x16_u |
0x9f |
|
i16x8.extmul_low_i8x16_s |
0x9c |
|
i16x8.extmul_low_i8x16_u |
0x9e |
|
i16x8.q15mulr_sat_s |
0x82 |
|
i32x4.extadd_pairwise_i16x8_s |
0x7e |
InProgress |
i32x4.extadd_pairwise_i16x8_u |
0x7f |
InProgress |
i32x4.extend_high_i16x8_s |
0xa8 |
|
i32x4.extend_high_i16x8_u |
0xaa |
|
i32x4.extend_low_i16x8_s |
0xa7 |
|
i32x4.extend_low_i16x8_u |
0xa9 |
|
i32x4.extmul_high_i16x8_s |
0xbd |
|
i32x4.extmul_high_i16x8_u |
0xbf |
|
i32x4.extmul_low_i16x8_s |
0xbc |
|
i32x4.extmul_low_i16x8_u |
0xbe |
|
i32x4.trunc_sat_f64x2_s_zero |
0xfc |
|
i32x4.trunc_sat_f64x2_u_zero |
0xfd |
|
i64x2.abs |
0xc0 |
|
i64x2.all_true |
0xc3 |
|
i64x2.eq |
0xd6 |
|
i64x2.extend_high_i32x4_s |
0xc8 |
|
i64x2.extend_high_i32x4_u |
0xca |
|
i64x2.extend_low_i32x4_s |
0xc7 |
|
i64x2.extend_low_i32x4_u |
0xc9 |
|
i64x2.extmul_high_i32x4_s |
0xdd |
|
i64x2.extmul_high_i32x4_u |
0xdf |
|
i64x2.extmul_low_i32x4_s |
0xdc |
|
i64x2.extmul_low_i32x4_u |
0xde |
|
i64x2.ge_s |
0xdb |
|
i64x2.gt_s |
0xd9 |
|
i64x2.le_s |
0xda |
|
i64x2.lt_s |
0xd8 |
|
i64x2.ne |
0xd7 |
|
v128.any_true |
0x53 |
|
v128.load16_lane |
0x55 |
|
v128.load32_lane |
0x56 |
|
v128.load64_lane |
0x57 |
|
v128.load8_lane |
0x54 |
|
v128.store16_lane |
0x59 |
|
v128.store32_lane |
0x5a |
|
v128.store64_lane |
0x5b |
|
v128.store8_lane |
0x58 |
|
|
|
|
cfallin commented on issue #2272:
@jlb6740 @abrown I think we can close this now, right?
abrown closed issue #2272:
Last Update: 1/14/2021
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load32_zero |
0xfc |
-- |
:+1: |
v128.load64_zero |
0xfd |
-- |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
:+1: |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
:+1: |
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
:+1: |
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
:+1: |
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
:+1: |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
------------ |
0x74 |
-- |
-- |
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
------------ |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
:+1: |
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
:+1: |
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
:+1: |
i16x8.shl |
0x8b |
:+1: |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
:+1: |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
------------ |
0x94 |
-- |
-- |
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
----------- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
:+1: |
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
:+1: |
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
:+1: |
i32x4.shl |
0xab |
:+1: |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
:+1: |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
i32x4.dot_i16x8_s |
0xba |
-- |
@abrown |
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
:+1: |
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
i64x2.bitmask |
0xc4 |
-- |
? |
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
i64x2.widen_low_i32x4_s |
0xc7 |
-- |
? |
i64x2.widen_high_i32x4_s |
0xc8 |
-- |
? |
i64x2.widen_low_i32x4_u |
0xc9 |
-- |
? |
i64x2.widen_high_i32x4_u |
0xca |
-- |
? |
i64x2.shl |
0xcb |
:+1: |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
:+1: |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
:+1: |
f32x4.floor |
0xd9 |
:question: |
:+1: |
f32x4.trunc |
0xda |
:question: |
:+1: |
f32x4.nearest |
0xdb |
:question: |
:+1: |
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
:+1: |
f32x4.pmax |
0xeb |
:question: |
:+1: |
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
:+1: |
f64x2.floor |
0xdd |
:question: |
:+1: |
f64x2.trunc |
0xde |
:question: |
:+1: |
f64x2.nearest |
0xdf |
:question: |
:+1: |
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
:+1: |
f64x2.pmax |
0xf7 |
:question: |
:+1: |
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:question: |
:+1: |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:question: |
:+1: |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
:+1: |
f32x4.convert_i32x4_u |
0xfb |
:question: |
:+1: |
Last updated: Dec 23 2024 at 12:05 UTC