bjorn3 opened issue #15057:
.clifTest Caseuse std::arch::aarch64::uint64x1_t; pub fn lane(_a: u8, b: uint64x1_t) -> uint64x1_t { b }Steps to Reproduce
- Compile with cg_clif
Expected Results
bis passed in a vector register.Actual Results
bis passed in an integer register asI64.by(1)returnsi64as type rather than ai64x1vector type.Versions and Environment
Cranelift version or commit: 0.137
Operating system: Linux
Architecture: arm64
Extra Info
Originally reported at https://github.com/rust-lang/rustc_codegen_cranelift/issues/1718
bjorn3 added the bug label to Issue #15057.
bjorn3 added the cranelift label to Issue #15057.
bjorn3 edited issue #15057:
.clifTest Caseuse std::arch::aarch64::uint64x1_t; #[unsafe(no_mangle)] fn lane(_a: u8, b: uint64x1_t) -> uint64x1_t { b }Steps to Reproduce
- Compile with cg_clif
Expected Results
bis passed in a vector register.Actual Results
bis passed in an integer register asI64.by(1)returnsi64as type rather than ai64x1vector type.Versions and Environment
Cranelift version or commit: 0.137
Operating system: Linux
Architecture: arm64
Extra Info
Originally reported at https://github.com/rust-lang/rustc_codegen_cranelift/issues/1718
bjorn3 edited issue #15057:
.clifTest Caseuse std::arch::aarch64::uint64x1_t; #[unsafe(no_mangle)] extern "C" fn lane(_a: u8, b: uint64x1_t) -> uint64x1_t { b }Steps to Reproduce
- Compile with cg_clif
Expected Results
bis passed in a vector register.Actual Results
bis passed in an integer register asI64.by(1)returnsi64as type rather than ai64x1vector type.Versions and Environment
Cranelift version or commit: 0.137
Operating system: Linux
Architecture: arm64
Extra Info
Originally reported at https://github.com/rust-lang/rustc_codegen_cranelift/issues/1718
Last updated: Oct 31 2026 at 23:03 UTC