Stream: git-wasmtime

Topic: wasmtime / issue #14691 Cranelift: miscompile on RV64, sw...

Wasmtime GitHub notifications bot (Oct 13 2026 at 01:49):

Takashiidobe edited issue #14691:

.clif Test Case

function %swizzle_splat_junk_upper_bits(i64) -> i8 {
block0(v0: i64):
    v1 = iconst.i64 0x0807060504030201
    v2 = splat.i64x2 v1
    v3 = bitcast.i8x16 little v2
    v4 = ireduce.i8 v0
    v5 = splat.i8x16 v4
    v6 = swizzle v3, v5
    v7 = extractlane v6, 0
    return v7
}
; run: %swizzle_splat_junk_upper_bits(0x100) == 1

Steps to Reproduce

• Compile this program for x86_64, aarch64, riscv, and s390x. riscv needs has_v.
• x86_64, aarch64, and s390x return 1 for this program. riscv is the only one that returns a 0.

Expected Results

• all targets should return 1.

Actual Results

• riscv is the only one to return 0.

Versions and Environment

Cranelift version or commit: 0.136.2.

Operating system: Linux

Architecture: I'm on x86_64, using qemu-static to emulate riscv

Extra Info

I assume the (rv_vrgather_vx x y (unmasked) ty) rule just needs to zext y to handle this bug.

To run this case in the browser I have a web tool that runs clif on the client side to demonstrate this on 0.136.2:

Risc-V (returns 0)
x86 (returns 1)

Wasmtime GitHub notifications bot (Oct 13 2026 at 14:38):

alexcrichton added the cranelift:area:riscv64 label to Issue #14691.

Wasmtime GitHub notifications bot (Oct 21 2026 at 18:09):

ColonelToad commented on issue #14691:

I’d like to work on this. My current plan is to zero-extend the splat index before vrgather.vx, add a runtest using ireduce.i8 with junk upper bits, and update the RISC-V ISA filetest. I’ll verify the assembly locally and rely on the RISC-V/QEMU CI job for the runtime check.

Wasmtime GitHub notifications bot (Oct 22 2026 at 20:50):

fitzgen closed issue #14691:

.clif Test Case

function %swizzle_splat_junk_upper_bits(i64) -> i8 {
block0(v0: i64):
    v1 = iconst.i64 0x0807060504030201
    v2 = splat.i64x2 v1
    v3 = bitcast.i8x16 little v2
    v4 = ireduce.i8 v0
    v5 = splat.i8x16 v4
    v6 = swizzle v3, v5
    v7 = extractlane v6, 0
    return v7
}
; run: %swizzle_splat_junk_upper_bits(0x100) == 1

Steps to Reproduce

• Compile this program for x86_64, aarch64, riscv, and s390x. riscv needs has_v.
• x86_64, aarch64, and s390x return 1 for this program. riscv is the only one that returns a 0.

Expected Results

• all targets should return 1.

Actual Results

• riscv is the only one to return 0.

Versions and Environment

Cranelift version or commit: 0.136.2.

Operating system: Linux

Architecture: I'm on x86_64, using qemu-static to emulate riscv

Extra Info

I assume the (rv_vrgather_vx x y (unmasked) ty) rule just needs to zext y to handle this bug.

To run this case in the browser I have a web tool that runs clif on the client side to demonstrate this on 0.136.2:

Risc-V (returns 0)
x86 (returns 1)

Last updated: Oct 31 2026 at 23:03 UTC