alexcrichton opened issue #14271:
This input:
<details>
;; Run test case test interpret test run set regalloc_checker=true set enable_alias_analysis=false set enable_nan_canonicalization=true set enable_llvm_abi_extensions=true set enable_multi_ret_implicit_sret=true set preserve_frame_pointers=true set machine_code_cfg_info=true target x86_64 has_sse3 has_ssse3 has_cmpxchg16b has_sse41 has_sse42 has_avx has_avx2 has_fma has_avx_vnni has_popcnt has_bmi1 has_bmi2 has_lzcnt function u1:0(i32x4, i32x4, i16x8, f64, f32x4, i64x2, i128 sext, i32 sext, i64 sext, f32, i16 uext, i64x2, i16 sext, i32x4, i8 sext, i8x16) -> i8x16, i32x4, i32x4, i32x4, i32x4, f64, i32x4, i32x4, i32x4, i32x4, i32x4, i32x4, i32x4, i8, i8, i32 system_v { ss0 = explicit_slot 120, align = 1024 ss1 = explicit_slot 120, align = 1024 ss2 = explicit_slot 120, align = 1024 ss3 = explicit_slot 2, align = 2 ss4 = explicit_slot 2, align = 2 ss5 = explicit_slot 8, align = 8 ss6 = explicit_slot 8, align = 8 sig0 = (f32) -> f32 system_v sig1 = (f64) -> f64 system_v sig2 = (f32) -> f32 system_v sig3 = (f64) -> f64 system_v sig4 = (f32) -> f32 system_v sig5 = (f64) -> f64 system_v fn0 = %CeilF32 sig0 fn1 = %CeilF64 sig1 fn2 = %FloorF32 sig2 fn3 = %FloorF64 sig3 fn4 = %TruncF32 sig4 fn5 = %TruncF64 sig5 block0(v0: i32x4, v1: i32x4, v2: i16x8, v3: f64, v4: f32x4, v5: i64x2, v6: i128, v7: i32, v8: i64, v9: f32, v10: i16, v11: i64x2, v12: i16, v13: i32x4, v14: i8, v15: i8x16): v175 -> v0 v191 -> v2 v192 -> v3 v193 -> v4 v172 -> v6 v187 -> v8 v182 -> v9 v194 -> v11 v195 -> v11 v190 -> v13 v197 -> v13 v196 -> v15 v270 = stack_addr.i64 ss6 store notrap aligned v8, v270 v142 = iconst.i64 0x7878_7878_7878_7878 v186 -> v142 v269 = stack_addr.i64 ss5 store notrap aligned v142, v269 ; v142 = 0x7878_7878_7878_7878 v143 = iconst.i8 0 v144 = iconst.i16 0 v145 = iconst.i32 0 v146 = iconst.i64 0 v147 = uextend.i128 v146 ; v146 = 0 v148 = stack_addr.i64 ss0 store notrap v147, v148 v149 = stack_addr.i64 ss0+16 store notrap v147, v149 v150 = stack_addr.i64 ss0+32 store notrap v147, v150 v151 = stack_addr.i64 ss0+48 store notrap v147, v151 v152 = stack_addr.i64 ss0+64 store notrap v147, v152 v153 = stack_addr.i64 ss0+80 store notrap v147, v153 v154 = stack_addr.i64 ss0+96 store notrap v147, v154 v155 = stack_addr.i64 ss0+112 store notrap v146, v155 ; v146 = 0 v156 = stack_addr.i64 ss1 store notrap v147, v156 v157 = stack_addr.i64 ss1+16 store notrap v147, v157 v158 = stack_addr.i64 ss1+32 store notrap v147, v158 v159 = stack_addr.i64 ss1+48 store notrap v147, v159 v160 = stack_addr.i64 ss1+64 store notrap v147, v160 v161 = stack_addr.i64 ss1+80 store notrap v147, v161 v162 = stack_addr.i64 ss1+96 store notrap v147, v162 v163 = stack_addr.i64 ss1+112 store notrap v146, v163 ; v146 = 0 v164 = stack_addr.i64 ss2 store notrap v147, v164 v165 = stack_addr.i64 ss2+16 store notrap v147, v165 v166 = stack_addr.i64 ss2+32 store notrap v147, v166 v167 = stack_addr.i64 ss2+48 store notrap v147, v167 v168 = stack_addr.i64 ss2+64 store notrap v147, v168 v169 = stack_addr.i64 ss2+80 store notrap v147, v169 v170 = stack_addr.i64 ss2+96 store notrap v147, v170 v171 = stack_addr.i64 ss2+112 store notrap v146, v171 ; v146 = 0 brif v10, block1(v14, v14, v14, v14, v12, v14, v10, v14, v12, v14, v10, v11, v10, v14), block1(v14, v14, v14, v14, v12, v14, v10, v14, v10, v14, v10, v11, v10, v14) block1(v16: i8, v17: i8, v18: i8, v19: i8, v20: i16, v21: i8, v22: i16, v23: i8, v24: i16, v25: i8, v26: i16, v27: i64x2, v28: i16, v29: i8) cold: v267 = stack_addr.i64 ss3 store notrap aligned v20, v267 v268 = stack_addr.i64 ss4 store notrap aligned v28, v268 v173 = bmask.i32 v172 v174 = stack_addr.i64 ss2+65 store.i32x4 v175, v174+35 v176 = select_spectre_guard v172, v173, v173 v177 = select_spectre_guard v172, v176, v176 v178 = select_spectre_guard v172, v177, v177 v179 = select_spectre_guard v172, v178, v178 v180 = select_spectre_guard v172, v179, v179 v181 = bxor.i32x4 v175, v175 v198 -> v181 v183 = func_addr.i64 fn0 v184 = call_indirect sig0, v183(v182), stack_map=[i64 @ ss6+0, i16 @ ss3+0, i16 @ ss4+0, i64 @ ss5+0] v185 = select_spectre_guard v172, v180, v180 v263 = stack_addr.i64 ss5 v264 = load.i64 notrap aligned v263 v265 = stack_addr.i64 ss6 v266 = load.i64 notrap aligned v265 v188, v189 = uadd_overflow v264, v266 v255 = stack_addr.i64 ss3 v256 = load.i16 notrap aligned v255 v257 = stack_addr.i64 ss3 v258 = load.i16 notrap aligned v257 v259 = stack_addr.i64 ss3 v260 = load.i16 notrap aligned v259 v261 = stack_addr.i64 ss4 v262 = load.i16 notrap aligned v261 brif v189, block2(v13, v2, v3, v4, v13, v6, v189, v185, v189, v188, v2, v184, v256, v2, v11, v258), block2(v0, v2, v3, v4, v0, v6, v189, v185, v189, v188, v2, v184, v260, v2, v27, v262) block2(v30: i32x4, v31: i16x8, v32: f64, v33: f32x4, v34: i32x4, v35: i128, v36: i8, v37: i32, v38: i8, v39: i64, v40: i16x8, v41: f32, v42: i16, v43: i16x8, v44: i64x2, v45: i16) cold: v200 -> v33 v199 -> v37 v201 -> v43 v206 -> v44 v227 -> v44 v228 -> v44 v203 -> v45 v225 -> v45 br_table v37, block3(v38, v38, v196, v196, v34, v34, v38, v198, v32, v34), [block11(v33, v33, v33, v33, v33, v33, v44, v33, v33, v33, v33, v45, v38, v196, v34, v198, v32, v37), block11(v33, v33, v33, v33, v33, v33, v195, v33, v33, v33, v33, v45, v38, v196, v34, v198, v32, v37), block3(v38, v38, v196, v196, v197, v198, v38, v197, v32, v198), block4(v197, v198, v198, v34, v38, v38, v38, v38, v37, v38, v38, v38, v38, v198, v34, v198, v32, v196), block5(v33, v33, v33, v33, v33, v33, v43, v38, v38, v38, v32, v198, v37, v196), block10(v33, v45, v33, v33, v33, v33, v33, v33, v195, v33, v33, v38, v196, v34, v198, v32, v37), block7(v37, v38, v45, v37, v38, v44, v38, v45, v38, v45, v38, v45, v38, v45, v33, v196, v34, v198, v32), block11(v33, v33, v33, v33, v33, v33, v44, v33, v33, v33, v33, v45, v38, v196, v34, v198, v32, v37), block5(v33, v33, v33, v33, v33, v33, v43, v38, v38, v38, v32, v198, v37, v196)] block3(v46: i8, v47: i8, v48: i8x16, v49: i8x16, v50: i32x4, v51: i32x4, v52: i8, v53: i32x4, v54: f64, v55: i32x4): jump block4(v53, v53, v53, v55, v52, v52, v52, v52, v199, v52, v52, v52, v52, v53, v53, v53, v54, v49) block4(v56: i32x4, v57: i32x4, v58: i32x4, v59: i32x4, v60: i8, v61: i8, v62: i8, v63: i8, v64: i32, v65: i8, v66: i8, v67: i8, v68: i8, v69: i32x4, v70: i32x4, v71: i32x4, v202: f64, v233: i8x16): jump block5(v200, v200, v200, v200, v200, v200, v201, v68, v68, v68, v202, v71, v64, v233) block5(v72: f32x4, v73: f32x4, v74: f32x4, v75: f32x4, v76: f32x4, v77: f32x4, v78: i16x8, v79: i8, v80: i8, v81: i8, v82: f64, v204: i32x4, v226: i32, v232: i8x16): v205 -> v226 jump block6(v81, v82, v203, v203, v81, v81, v78, v78, v78, v204) block6(v83: i8, v84: f64, v85: i16, v86: i16, v87: i8, v88: i8, v89: i16x8, v90: i16x8, v91: i16x8, v92: i32x4): jump block7(v205, v88, v86, v205, v88, v206, v88, v86, v88, v86, v88, v86, v88, v86, v77, v232, v92, v204, v84) block7(v93: i32, v94: i8, v95: i16, v96: i32, v97: i8, v98: i64x2, v99: i8, v100: i16, v101: i8, v102: i16, v103: i8, v104: i16, v105: i8, v106: i16, v207: f32x4, v231: i8x16, v238: i32x4, v243: i32x4, v248: f64): v211 -> v96 v209 -> v98 v214 -> v98 v210 -> v106 v213 -> v106 v208 -> v207 v212 -> v207 br_table v96, block8(v105), [block13(v105, v231, v238, v243, v248, v96), block13(v105, v231, v238, v243, v248, v96), block13(v105, v231, v238, v243, v248, v96), block13(v105, v231, v238, v243, v248, v96), block13(v105, v231, v238, v243, v248, v96), block13(v105, v231, v238, v243, v248, v96), block13(v105, v231, v238, v243, v248, v96), block13(v105, v231, v238, v243, v248, v96), block11(v207, v207, v207, v207, v207, v207, v98, v207, v207, v207, v207, v106, v105, v231, v238, v243, v248, v96), block13(v105, v231, v238, v243, v248, v96)] block8(v107: i8): v215 -> v107 br_table v211, block9, [block11(v208, v208, v208, v208, v208, v208, v209, v208, v208, v208, v208, v210, v107, v231, v238, v243, v248, v211), block11(v208, v208, v208, v208, v208, v208, v209, v208, v208, v208, v208, v210, v107, v231, v238, v243, v248, v211), block9, block10(v208, v210, v208, v208, v208, v208, v208, v208, v209, v208, v208, v107, v231, v238, v243, v248, v211), block10(v208, v210, v208, v208, v208, v208, v208, v208, v209, v208, v208, v107, v231, v238, v243, v248, v211), block10(v208, v210, v208, v208, v208, v208, v208, v208, v209, v208, v208, v107, v231, v238, v243, v248, v211), block10(v208, v210, v208, v208, v208, v208, v208, v208, v209, v208, v208, v107, v231, v238, v243, v248, v211), block10(v208, v210, v208, v208, v208, v208, v208, v208, v209, v208, v208, v107, v231, v238, v243, v248, v211), block10(v208, v210, v208, v208, v208, v208, v208, v208, v209, v208, v208, v107, v231, v238, v243, v248, v211)] block9 cold: brif.i8 v215, block10(v212, v213, v212, v212, v212, v212, v212, v212, v214, v212, v212, v215, v231, v238, v243, v248, v211), block11(v212, v212, v212, v212, v212, v212, v214, v212, v212, v212, v212, v213, v215, v231, v238, v243, v248, v211) block10(v108: f32x4, v109: i16, v110: f32x4, v111: f32x4, v112: f32x4, v113: f32x4, v114: f32x4, v115: f32x4, v116: i64x2, v117: f32x4, v118: f32x4, v216: i8, v230: i8x16, v237: i32x4, v242: i32x4, v247: f64, v252: i32) cold: brif v216, block11(v118, v118, v118, v118, v118, v118, v116, v118, v118, v118, v118, v109, v216, v [message truncated]
alexcrichton added the fuzz-bug label to Issue #14271.
cfallin commented on issue #14271:
Thanks, taking a look...
fitzgen closed issue #14271:
This input:
<details>
;; Run test case test interpret test run set regalloc_checker=true set enable_alias_analysis=false set enable_nan_canonicalization=true set enable_llvm_abi_extensions=true set enable_multi_ret_implicit_sret=true set preserve_frame_pointers=true set machine_code_cfg_info=true target x86_64 has_sse3 has_ssse3 has_cmpxchg16b has_sse41 has_sse42 has_avx has_avx2 has_fma has_avx_vnni has_popcnt has_bmi1 has_bmi2 has_lzcnt function u1:0(i32x4, i32x4, i16x8, f64, f32x4, i64x2, i128 sext, i32 sext, i64 sext, f32, i16 uext, i64x2, i16 sext, i32x4, i8 sext, i8x16) -> i8x16, i32x4, i32x4, i32x4, i32x4, f64, i32x4, i32x4, i32x4, i32x4, i32x4, i32x4, i32x4, i8, i8, i32 system_v { ss0 = explicit_slot 120, align = 1024 ss1 = explicit_slot 120, align = 1024 ss2 = explicit_slot 120, align = 1024 ss3 = explicit_slot 2, align = 2 ss4 = explicit_slot 2, align = 2 ss5 = explicit_slot 8, align = 8 ss6 = explicit_slot 8, align = 8 sig0 = (f32) -> f32 system_v sig1 = (f64) -> f64 system_v sig2 = (f32) -> f32 system_v sig3 = (f64) -> f64 system_v sig4 = (f32) -> f32 system_v sig5 = (f64) -> f64 system_v fn0 = %CeilF32 sig0 fn1 = %CeilF64 sig1 fn2 = %FloorF32 sig2 fn3 = %FloorF64 sig3 fn4 = %TruncF32 sig4 fn5 = %TruncF64 sig5 block0(v0: i32x4, v1: i32x4, v2: i16x8, v3: f64, v4: f32x4, v5: i64x2, v6: i128, v7: i32, v8: i64, v9: f32, v10: i16, v11: i64x2, v12: i16, v13: i32x4, v14: i8, v15: i8x16): v175 -> v0 v191 -> v2 v192 -> v3 v193 -> v4 v172 -> v6 v187 -> v8 v182 -> v9 v194 -> v11 v195 -> v11 v190 -> v13 v197 -> v13 v196 -> v15 v270 = stack_addr.i64 ss6 store notrap aligned v8, v270 v142 = iconst.i64 0x7878_7878_7878_7878 v186 -> v142 v269 = stack_addr.i64 ss5 store notrap aligned v142, v269 ; v142 = 0x7878_7878_7878_7878 v143 = iconst.i8 0 v144 = iconst.i16 0 v145 = iconst.i32 0 v146 = iconst.i64 0 v147 = uextend.i128 v146 ; v146 = 0 v148 = stack_addr.i64 ss0 store notrap v147, v148 v149 = stack_addr.i64 ss0+16 store notrap v147, v149 v150 = stack_addr.i64 ss0+32 store notrap v147, v150 v151 = stack_addr.i64 ss0+48 store notrap v147, v151 v152 = stack_addr.i64 ss0+64 store notrap v147, v152 v153 = stack_addr.i64 ss0+80 store notrap v147, v153 v154 = stack_addr.i64 ss0+96 store notrap v147, v154 v155 = stack_addr.i64 ss0+112 store notrap v146, v155 ; v146 = 0 v156 = stack_addr.i64 ss1 store notrap v147, v156 v157 = stack_addr.i64 ss1+16 store notrap v147, v157 v158 = stack_addr.i64 ss1+32 store notrap v147, v158 v159 = stack_addr.i64 ss1+48 store notrap v147, v159 v160 = stack_addr.i64 ss1+64 store notrap v147, v160 v161 = stack_addr.i64 ss1+80 store notrap v147, v161 v162 = stack_addr.i64 ss1+96 store notrap v147, v162 v163 = stack_addr.i64 ss1+112 store notrap v146, v163 ; v146 = 0 v164 = stack_addr.i64 ss2 store notrap v147, v164 v165 = stack_addr.i64 ss2+16 store notrap v147, v165 v166 = stack_addr.i64 ss2+32 store notrap v147, v166 v167 = stack_addr.i64 ss2+48 store notrap v147, v167 v168 = stack_addr.i64 ss2+64 store notrap v147, v168 v169 = stack_addr.i64 ss2+80 store notrap v147, v169 v170 = stack_addr.i64 ss2+96 store notrap v147, v170 v171 = stack_addr.i64 ss2+112 store notrap v146, v171 ; v146 = 0 brif v10, block1(v14, v14, v14, v14, v12, v14, v10, v14, v12, v14, v10, v11, v10, v14), block1(v14, v14, v14, v14, v12, v14, v10, v14, v10, v14, v10, v11, v10, v14) block1(v16: i8, v17: i8, v18: i8, v19: i8, v20: i16, v21: i8, v22: i16, v23: i8, v24: i16, v25: i8, v26: i16, v27: i64x2, v28: i16, v29: i8) cold: v267 = stack_addr.i64 ss3 store notrap aligned v20, v267 v268 = stack_addr.i64 ss4 store notrap aligned v28, v268 v173 = bmask.i32 v172 v174 = stack_addr.i64 ss2+65 store.i32x4 v175, v174+35 v176 = select_spectre_guard v172, v173, v173 v177 = select_spectre_guard v172, v176, v176 v178 = select_spectre_guard v172, v177, v177 v179 = select_spectre_guard v172, v178, v178 v180 = select_spectre_guard v172, v179, v179 v181 = bxor.i32x4 v175, v175 v198 -> v181 v183 = func_addr.i64 fn0 v184 = call_indirect sig0, v183(v182), stack_map=[i64 @ ss6+0, i16 @ ss3+0, i16 @ ss4+0, i64 @ ss5+0] v185 = select_spectre_guard v172, v180, v180 v263 = stack_addr.i64 ss5 v264 = load.i64 notrap aligned v263 v265 = stack_addr.i64 ss6 v266 = load.i64 notrap aligned v265 v188, v189 = uadd_overflow v264, v266 v255 = stack_addr.i64 ss3 v256 = load.i16 notrap aligned v255 v257 = stack_addr.i64 ss3 v258 = load.i16 notrap aligned v257 v259 = stack_addr.i64 ss3 v260 = load.i16 notrap aligned v259 v261 = stack_addr.i64 ss4 v262 = load.i16 notrap aligned v261 brif v189, block2(v13, v2, v3, v4, v13, v6, v189, v185, v189, v188, v2, v184, v256, v2, v11, v258), block2(v0, v2, v3, v4, v0, v6, v189, v185, v189, v188, v2, v184, v260, v2, v27, v262) block2(v30: i32x4, v31: i16x8, v32: f64, v33: f32x4, v34: i32x4, v35: i128, v36: i8, v37: i32, v38: i8, v39: i64, v40: i16x8, v41: f32, v42: i16, v43: i16x8, v44: i64x2, v45: i16) cold: v200 -> v33 v199 -> v37 v201 -> v43 v206 -> v44 v227 -> v44 v228 -> v44 v203 -> v45 v225 -> v45 br_table v37, block3(v38, v38, v196, v196, v34, v34, v38, v198, v32, v34), [block11(v33, v33, v33, v33, v33, v33, v44, v33, v33, v33, v33, v45, v38, v196, v34, v198, v32, v37), block11(v33, v33, v33, v33, v33, v33, v195, v33, v33, v33, v33, v45, v38, v196, v34, v198, v32, v37), block3(v38, v38, v196, v196, v197, v198, v38, v197, v32, v198), block4(v197, v198, v198, v34, v38, v38, v38, v38, v37, v38, v38, v38, v38, v198, v34, v198, v32, v196), block5(v33, v33, v33, v33, v33, v33, v43, v38, v38, v38, v32, v198, v37, v196), block10(v33, v45, v33, v33, v33, v33, v33, v33, v195, v33, v33, v38, v196, v34, v198, v32, v37), block7(v37, v38, v45, v37, v38, v44, v38, v45, v38, v45, v38, v45, v38, v45, v33, v196, v34, v198, v32), block11(v33, v33, v33, v33, v33, v33, v44, v33, v33, v33, v33, v45, v38, v196, v34, v198, v32, v37), block5(v33, v33, v33, v33, v33, v33, v43, v38, v38, v38, v32, v198, v37, v196)] block3(v46: i8, v47: i8, v48: i8x16, v49: i8x16, v50: i32x4, v51: i32x4, v52: i8, v53: i32x4, v54: f64, v55: i32x4): jump block4(v53, v53, v53, v55, v52, v52, v52, v52, v199, v52, v52, v52, v52, v53, v53, v53, v54, v49) block4(v56: i32x4, v57: i32x4, v58: i32x4, v59: i32x4, v60: i8, v61: i8, v62: i8, v63: i8, v64: i32, v65: i8, v66: i8, v67: i8, v68: i8, v69: i32x4, v70: i32x4, v71: i32x4, v202: f64, v233: i8x16): jump block5(v200, v200, v200, v200, v200, v200, v201, v68, v68, v68, v202, v71, v64, v233) block5(v72: f32x4, v73: f32x4, v74: f32x4, v75: f32x4, v76: f32x4, v77: f32x4, v78: i16x8, v79: i8, v80: i8, v81: i8, v82: f64, v204: i32x4, v226: i32, v232: i8x16): v205 -> v226 jump block6(v81, v82, v203, v203, v81, v81, v78, v78, v78, v204) block6(v83: i8, v84: f64, v85: i16, v86: i16, v87: i8, v88: i8, v89: i16x8, v90: i16x8, v91: i16x8, v92: i32x4): jump block7(v205, v88, v86, v205, v88, v206, v88, v86, v88, v86, v88, v86, v88, v86, v77, v232, v92, v204, v84) block7(v93: i32, v94: i8, v95: i16, v96: i32, v97: i8, v98: i64x2, v99: i8, v100: i16, v101: i8, v102: i16, v103: i8, v104: i16, v105: i8, v106: i16, v207: f32x4, v231: i8x16, v238: i32x4, v243: i32x4, v248: f64): v211 -> v96 v209 -> v98 v214 -> v98 v210 -> v106 v213 -> v106 v208 -> v207 v212 -> v207 br_table v96, block8(v105), [block13(v105, v231, v238, v243, v248, v96), block13(v105, v231, v238, v243, v248, v96), block13(v105, v231, v238, v243, v248, v96), block13(v105, v231, v238, v243, v248, v96), block13(v105, v231, v238, v243, v248, v96), block13(v105, v231, v238, v243, v248, v96), block13(v105, v231, v238, v243, v248, v96), block13(v105, v231, v238, v243, v248, v96), block11(v207, v207, v207, v207, v207, v207, v98, v207, v207, v207, v207, v106, v105, v231, v238, v243, v248, v96), block13(v105, v231, v238, v243, v248, v96)] block8(v107: i8): v215 -> v107 br_table v211, block9, [block11(v208, v208, v208, v208, v208, v208, v209, v208, v208, v208, v208, v210, v107, v231, v238, v243, v248, v211), block11(v208, v208, v208, v208, v208, v208, v209, v208, v208, v208, v208, v210, v107, v231, v238, v243, v248, v211), block9, block10(v208, v210, v208, v208, v208, v208, v208, v208, v209, v208, v208, v107, v231, v238, v243, v248, v211), block10(v208, v210, v208, v208, v208, v208, v208, v208, v209, v208, v208, v107, v231, v238, v243, v248, v211), block10(v208, v210, v208, v208, v208, v208, v208, v208, v209, v208, v208, v107, v231, v238, v243, v248, v211), block10(v208, v210, v208, v208, v208, v208, v208, v208, v209, v208, v208, v107, v231, v238, v243, v248, v211), block10(v208, v210, v208, v208, v208, v208, v208, v208, v209, v208, v208, v107, v231, v238, v243, v248, v211), block10(v208, v210, v208, v208, v208, v208, v208, v208, v209, v208, v208, v107, v231, v238, v243, v248, v211)] block9 cold: brif.i8 v215, block10(v212, v213, v212, v212, v212, v212, v212, v212, v214, v212, v212, v215, v231, v238, v243, v248, v211), block11(v212, v212, v212, v212, v212, v212, v214, v212, v212, v212, v212, v213, v215, v231, v238, v243, v248, v211) block10(v108: f32x4, v109: i16, v110: f32x4, v111: f32x4, v112: f32x4, v113: f32x4, v114: f32x4, v115: f32x4, v116: i64x2, v117: f32x4, v118: f32x4, v216: i8, v230: i8x16, v237: i32x4, v242: i32x4, v247: f64, v252: i32) cold: brif v216, block11(v118, v118, v118, v118, v118, v118, v116, v118, v118, v118, v118, v109, v216, v230, [message truncated]
Last updated: Sep 20 2026 at 18:08 UTC