alexcrichton opened issue #13076:
Currently, for example, this is what Cranelift generates:
function %atomic_rmw_add_i8(i64, i8) { block0(v0: i64, v1: i8): v2 = atomic_rmw.i8 add v0, v1 return } ; VCode: ; block0: ; andi a2,a0,3 ; slli a2,a2,3 ; andi a0,a0,-4 ; atomic_rmw.i8 add a4,a1,(a0)##t0=a3 offset=a2 ; ret ; ; Disassembled: ; block0: ; offset 0x0 ; andi a2, a0, 3 ; slli a2, a2, 3 ; andi a0, a0, -4 ; lr.w.aqrl a4, (a0) ; trap: heap_oob ; srl a4, a4, a2 ; andi a4, a4, 0xff ; add a3, a4, a1 ; lr.w.aqrl t5, (a0) ; trap: heap_oob ; addi t6, zero, 0xff ; sll t6, t6, a2 ; not t6, t6 ; and t5, t5, t6 ; andi t6, a3, 0xff ; sll t6, t6, a2 ; or t5, t5, t6 ; sc.w.aqrl a3, t5, (a0) ; trap: heap_oob ; bnez a3, -0x34 ; retThis incorrectly contains two
lr.w.aqrlvalues instead of one. Thesc.w.aqrlat the end is conditional on the most recentlr.w, not the first.
alexcrichton added the cranelift:area:riscv64 label to Issue #13076.
alexcrichton added the wasm-proposal:threads label to Issue #13076.
Last updated: May 03 2026 at 22:13 UTC