Stream: git-wasmtime

Topic: wasmtime / issue #13076 riscv64: Atomics for 8/16-bit val...

Wasmtime GitHub notifications bot (Apr 13 2026 at 19:22):

alexcrichton opened issue #13076:

Currently, for example, this is what Cranelift generates:

function %atomic_rmw_add_i8(i64, i8) {
block0(v0: i64, v1: i8):
    v2 = atomic_rmw.i8 add v0, v1
    return
}

; VCode:
; block0:
;   andi a2,a0,3
;   slli a2,a2,3
;   andi a0,a0,-4
;   atomic_rmw.i8 add a4,a1,(a0)##t0=a3 offset=a2
;   ret
;
; Disassembled:
; block0: ; offset 0x0
;   andi a2, a0, 3
;   slli a2, a2, 3
;   andi a0, a0, -4
;   lr.w.aqrl a4, (a0) ; trap: heap_oob
;   srl a4, a4, a2
;   andi a4, a4, 0xff
;   add a3, a4, a1
;   lr.w.aqrl t5, (a0) ; trap: heap_oob
;   addi t6, zero, 0xff
;   sll t6, t6, a2
;   not t6, t6
;   and t5, t5, t6
;   andi t6, a3, 0xff
;   sll t6, t6, a2
;   or t5, t5, t6
;   sc.w.aqrl a3, t5, (a0) ; trap: heap_oob
;   bnez a3, -0x34
;   ret

This incorrectly contains two lr.w.aqrl values instead of one. The sc.w.aqrl at the end is conditional on the most recent lr.w, not the first.

Wasmtime GitHub notifications bot (Apr 13 2026 at 19:22):

alexcrichton added the cranelift:area:riscv64 label to Issue #13076.

Wasmtime GitHub notifications bot (Apr 13 2026 at 19:22):

alexcrichton added the wasm-proposal:threads label to Issue #13076.

Wasmtime GitHub notifications bot (May 16 2026 at 23:44):

surajk-m commented on issue #13076:

Hey @alexcrichton, please review the PR.

While looking into this, I also noticed that AtomicCas has the same shape for sub-word types. Specifically, the // reload value to t0. block in the ty.bits() < 32 path issues a second lr.w.aqrl before AtomicOP::merge.

let store_value = if ty.bits() < 32 {
    // reload value to t0.
    Inst::Atomic {
        op: AtomicOP::load_op(ty),  // second lr.w.aqrl
        rd: t0,
        addr,
        src: zero_reg(),
        amo: AMO::SeqCst,
    }
    .emit(sink, emit_info, state);
    AtomicOP::merge(t0, writable_spilltmp_reg(), offset, v, ty)...

Wasmtime GitHub notifications bot (May 18 2026 at 19:39):

cfallin closed issue #13076:

Currently, for example, this is what Cranelift generates:

function %atomic_rmw_add_i8(i64, i8) {
block0(v0: i64, v1: i8):
    v2 = atomic_rmw.i8 add v0, v1
    return
}

; VCode:
; block0:
;   andi a2,a0,3
;   slli a2,a2,3
;   andi a0,a0,-4
;   atomic_rmw.i8 add a4,a1,(a0)##t0=a3 offset=a2
;   ret
;
; Disassembled:
; block0: ; offset 0x0
;   andi a2, a0, 3
;   slli a2, a2, 3
;   andi a0, a0, -4
;   lr.w.aqrl a4, (a0) ; trap: heap_oob
;   srl a4, a4, a2
;   andi a4, a4, 0xff
;   add a3, a4, a1
;   lr.w.aqrl t5, (a0) ; trap: heap_oob
;   addi t6, zero, 0xff
;   sll t6, t6, a2
;   not t6, t6
;   and t5, t5, t6
;   andi t6, a3, 0xff
;   sll t6, t6, a2
;   or t5, t5, t6
;   sc.w.aqrl a3, t5, (a0) ; trap: heap_oob
;   bnez a3, -0x34
;   ret

This incorrectly contains two lr.w.aqrl values instead of one. The sc.w.aqrl at the end is conditional on the most recent lr.w, not the first.

Last updated: Jun 01 2026 at 09:49 UTC