Wasmtime GitHub notifications bot (Apr 09 2026 at 14:52): Wasmtime GitHub notifications bot (Apr 09 2026 at 14:52):alexcrichton opened issue #13006:
This is an accidental regression from #12948
this input:
<details>
;;test interpret test run set opt_level=speed set bb_padding_log2_minus_one=3 set regalloc_checker=true set enable_nan_canonicalization=true set enable_llvm_abi_extensions=true set enable_multi_ret_implicit_sret=true set machine_code_cfg_info=true target x86_64 has_sse3 has_ssse3 has_cmpxchg16b has_sse41 has_sse42 has_avx has_avx2 has_fma has_popcnt has_bmi1 has_bmi2 has_lzcnt function %a(i32x4, i16x8, f64, f32x4, i64x2, i128 sext, i32 sext, i64 sext, f32, i16 uext, i64x2, i16 uext, i32x4, i8 sext, i8x16, i8x16) -> i128 sext, i16x8, f64, f32x4, i16 uext, i128, i8 uext, i8 sext, f32x4, i8 sext, i64 sext, i8 sext, i8 uext, i32 sext, i8, i8 sext system_v { sig0 = (f32) -> f32 system_v sig1 = (f64) -> f64 system_v sig2 = (f32) -> f32 system_v sig3 = (f64) -> f64 system_v sig4 = (f32) -> f32 system_v sig5 = (f64) -> f64 system_v fn0 = %CeilF32 sig0 fn1 = %CeilF64 sig1 fn2 = %FloorF32 sig2 fn3 = %FloorF64 sig3 fn4 = %TruncF32 sig4 fn5 = %TruncF64 sig5 block0(v0: i32x4, v1: i16x8, v2: f64, v3: f32x4, v4: i64x2, v5: i128, v6: i32, v7: i64, v8: f32, v9: i16, v10: i64x2, v11: i16, v12: i32x4, v13: i8, v14: i8x16, v15: i8x16): v195 -> v6 v140 -> v7 v182 -> v7 v244 -> v7 v223 -> v8 v241 -> v10 v208 -> v11 v272 -> v12 v227 -> v13 v240 -> v13 v236 -> v14 v231 -> v15 v94 = iconst.i8 0 v95 = iconst.i16 0 v96 = iconst.i32 0 v97 = iconst.i64 0 v98 = uextend.i128 v97 ; v97 = 0 v99 = rotr v9, v7 v100 = rotr v99, v7 v101 = rotr v100, v7 v102 = rotr v101, v7 v103 = rotr v102, v7 v104 = rotr v103, v7 v105 = rotr v104, v7 v106 = rotr v105, v7 v107 = rotr v106, v7 v108 = rotr v107, v7 v109 = rotr v108, v7 v110 = rotr v109, v7 v111 = rotr v110, v7 v112 = rotr v111, v7 v113 = rotr v112, v7 v114 = rotr v113, v7 v115 = rotr v11, v7 v116 = rotr v115, v7 v117 = rotr v116, v7 v118 = rotr v117, v7 v119 = rotr v118, v7 v120 = rotr v119, v7 v121 = rotr v120, v7 v122 = rotr v121, v7 v123 = rotr v122, v7 v124 = rotr v123, v7 v125 = rotr v124, v7 v126 = rotr v125, v7 v127 = rotr v126, v7 v128 = rotr v127, v7 v129 = rotr v128, v7 v130 = rotr v129, v7 v131 = rotr v130, v7 v132 = rotr v131, v7 v133 = rotr v132, v7 v134 = rotr v133, v7 v135 = rotr v134, v7 v136 = rotr v135, v7 v137 = rotr v136, v7 v138 = rotr v137, v7 v139 -> v138 jump block1(v4, v0, v1, v5, v2, v0, v0, v0, v0, v0, v0, v0, v0, v0, v3, v0) block1(v16: i64x2, v17: i32x4, v18: i16x8, v19: i128, v20: f64, v21: i32x4, v22: i32x4, v23: i32x4, v24: i32x4, v25: i32x4, v26: i32x4, v27: i32x4, v28: i32x4, v29: i32x4, v30: f32x4, v31: i32x4): v259 -> v18 v242 -> v19 v273 -> v30 v141 = rotr.i16 v139, v140 v142 = rotr v141, v140 v143 = rotr v142, v140 v144 = rotr v143, v140 v145 = rotr v144, v140 v146 = rotr v145, v140 v147 = rotr v146, v140 v148 = rotr v147, v140 v149 = rotr v148, v140 v150 = rotr v149, v140 v151 = rotr v150, v140 v152 = rotr v151, v140 v153 = rotr v152, v140 v154 = rotr v153, v140 v155 = rotr v154, v140 v156 = rotr v155, v140 v157 = rotr v156, v140 v158 = rotr v157, v140 v159 = rotr v158, v140 v160 = rotr v159, v140 v161 = rotr v160, v140 v162 = rotr v161, v140 v163 = rotr v162, v140 v164 = rotr v163, v140 v165 = select v164, v16, v16 v197 -> v165 v166 = rotr v164, v140 v167 = rotr v166, v140 v168 = rotr v167, v140 v169 = rotr v168, v140 v170 = rotr v169, v140 v171 = rotr v170, v140 v172 = rotr v171, v140 v173 = rotr v172, v140 v174 = rotr v173, v140 v175 = rotr v174, v140 v176 = rotr v175, v140 v177 = rotr v176, v140 v178 = rotr v177, v140 v179 = rotr v178, v140 v180 = rotr v179, v140 v181 -> v180 jump block2(v20, v20, v20, v20, v20, v20, v20, v20, v20, v20) block2(v32: f64, v33: f64, v34: f64, v35: f64, v36: f64, v37: f64, v38: f64, v39: f64, v40: f64, v41: f64): v183 = rotr.i16 v181, v182 v184 = rotr v183, v182 v185 = rotr v184, v182 v186 = rotr v185, v182 v187 = rotr v186, v182 v188 = rotr v187, v182 v189 = rotr v188, v182 v190 = rotr v189, v182 v191 = rotr v190, v182 v192 = rotr v191, v182 v193 = rotr v192, v182 v194 = rotr v193, v182 v196 = bor_not.i32 v195, v195 v510 -> v196 v532 -> v196 v533 -> v196 v544 -> v196 v198 = isub.i64x2 v197, v197 v255 -> v198 v199 = rotr v194, v182 v200 = rotr v199, v182 v201 = rotr v200, v182 v202 = rotr v201, v182 v203 = rotr v202, v182 v204 = rotr v203, v182 v205 = rotr v204, v182 v206 = rotr v205, v182 v207 = rotr v206, v182 v209 = select_spectre_guard.i16 v196, v208, v208 v210 = select_spectre_guard v196, v209, v209 v211 = select_spectre_guard v196, v210, v210 v212 = select_spectre_guard v196, v211, v211 v213 = select_spectre_guard v196, v212, v212 v214 = select_spectre_guard v196, v213, v213 v215 = select_spectre_guard v196, v214, v214 v216 = select_spectre_guard v196, v215, v215 v217 = select_spectre_guard v196, v216, v216 v218 = select_spectre_guard v196, v217, v217 v219 = select_spectre_guard v196, v218, v218 v220 = select_spectre_guard v196, v219, v219 v221 = select_spectre_guard v196, v220, v220 v222 = select_spectre_guard v196, v221, v221 v224 = call fn0(v223) v261 -> v224 v225 = sshr v222, v222 v226 = sshr v225, v225 brif.i8 v227, block3(v41, v41, v225, v41, v41, v41, v41, v41, v41, v41), block6(v224, v182, v18, v226, v227, v225, v198, v19, v41, v30) block3(v42: f64, v43: f64, v44: i16, v45: f64, v46: f64, v47: f64, v48: f64, v49: f64, v50: f64, v51: f64): v228 = sshr v44, v44 v229 = sshr v228, v228 v230 = sshr v229, v229 v274 -> v230 v232 = band_not.i8x16 v231, v231 v233 = band_not v232, v232 v234 = band_not v233, v233 v235 = band_not v234, v234 v237 = band_not.i8x16 v236, v236 v238 = band_not v237, v237 v239 = band_not v238, v238 jump block4(v51, v51, v51, v240, v240, v241, v230, v239, v239, v239) block4(v52: f64, v53: f64, v54: f64, v55: i8, v56: i8, v57: i64x2, v58: i16, v59: i8x16, v60: i8x16, v61: i8x16): v243 = bmask.i8 v242 v245 = select_spectre_guard v244, v58, v58 v246 = bmask.i8 v242 v247 = bmask.i8 v242 v248 = bmask.i8 v242 v249 = bmask.i8 v242 v250 = uextend.i128 v245 v251 = band_not v54, v54 v252 = band_not v251, v251 v253 = band_not v252, v252 v254 = band_not v253, v253 v256 = sshr.i64x2 v255, v244 v257 = band_not v254, v254 v258 = band_not v257, v257 v260 = vany_true.i16x8 v259 v262 = func_addr.i64 fn0 v263 = call_indirect sig0, v262(v261) v264 = select v244, v57, v256 v265 = func_addr.i64 fn0 v266 = call_indirect sig0, v265(v263) v267 = select v244, v264, v256 v268 = func_addr.i64 fn0 v269 = call_indirect sig0, v268(v266) v275 -> v269 v270 = select v244, v267, v256 v545 = fcmp ne v258, v258 v546 = f64const -0x1.0000000000000p0 v547 = f64const 0x1.0000000000000p64 v548 = fcmp le v258, v546 ; v546 = -0x1.0000000000000p0 v549 = fcmp ge v258, v547 ; v547 = 0x1.0000000000000p64 v550 = bor v548, v549 v551 = bor v545, v550 v552 = f64const 0x1.0000000000000p0 v553 = select v551, v552, v258 ; v552 = 0x1.0000000000000p0 v271 = fcvt_to_uint.i64 v553 jump block5(v60, v61, v60, v61, v272, v273, v273, v256, v259, v259, v259, v259, v259, v274, v259, v250) block5(v62: i8x16, v63: i8x16, v64: i8x16, v65: i8x16, v66: i32x4, v67: f32x4, v68: f32x4, v69: i64x2, v70: i16x8, v71: i16x8, v72: i16x8, v73: i16x8, v74: i16x8, v75: i16, v76: i16x8, v77: i128): v276 = func_addr.i64 fn0 v277 = call_indirect sig0, v276(v275) v278 = iconst.i64 0x00fa_0000_7300_0092 v279 = iconst.i64 0x3138_3835_3404_0402 v280 = iconcat v278, v279 ; v278 = 0x00fa_0000_7300_0092, v279 = 0x3138_3835_3404_0402 v281 = icmp uge v77, v280 brif v281, block11, block10 block11: v282 = iconst.i64 0x0100_0000_003e_0100 v283 = iconst.i64 -7451204483956080384 v284 = iconcat v282, v283 ; v282 = 0x0100_0000_003e_0100, v283 = -7451204483956080384 v285 = icmp.i128 uge v77, v284 brif v285, block13, block12 block13: v286 = iconst.i64 -3617009525824946176 v287 = iconst.i64 -3617008641903833820 v288 = iconcat v286, v287 ; v286 = -3617009525824946176, v287 = -3617008641903833820 v289 = icmp.i128 uge v77, v288 brif v289, block15, block14 block15: v290 = iconst.i64 0x0707_0707_0707_0707 v291 = iconst.i64 -2232933263481567481 v292 = iconcat v290, v291 ; v290 = 0x0707_0707_0707_0707, v291 = -2232933263481567481 v293 = icmp.i128 uge v77, v292 brif v293, block17, block16 block17: v294 = iconst.i64 -2170205185142300191 v295 = iconst.i64 -2173864359839538719 v296 = iconcat v294, v295 ; v294 = -2170205185142300191, v295 = -2173864359839538719 v297 = icmp.i128 eq v77, v296 brif v297, block8(v277, v260, v274, v76, v256, v77, v258, v68, v271), block18 block18: v298 = iconst.i64 0x0707_0707_0707_0707 v299 = iconst.i64 -2232933263481567481 v300 = iconcat v298, v299 ; v298 = 0x0707_0707_0707_0707, v299 = -2232933263481567481 v301 = icmp.i128 eq v77, v300 brif v301, block8(v277, v260, v274, v76, v256, v77, v258, v68, v271), block6(v277, v271, v76, v75, v260, v274, v256, v77, v258, v68) block16: v302 = iconst.i64 -3617008643992366767 v303 = iconst.i64 -3616973457531744819 v304 = iconcat v302, v303 ; v302 = -3 [message truncated]
Wasmtime GitHub notifications bot (Apr 09 2026 at 14:52):alexcrichton added the fuzz-bug label to Issue #13006.
Wasmtime GitHub notifications bot (Apr 10 2026 at 13:33):alexcrichton commented on issue #13006:
Fixed in #13031, thanks!
Wasmtime GitHub notifications bot (Apr 10 2026 at 13:33):alexcrichton closed issue #13006:
This is an accidental regression from #12948
this input:
<details>
;;test interpret test run set opt_level=speed set bb_padding_log2_minus_one=3 set regalloc_checker=true set enable_nan_canonicalization=true set enable_llvm_abi_extensions=true set enable_multi_ret_implicit_sret=true set machine_code_cfg_info=true target x86_64 has_sse3 has_ssse3 has_cmpxchg16b has_sse41 has_sse42 has_avx has_avx2 has_fma has_popcnt has_bmi1 has_bmi2 has_lzcnt function %a(i32x4, i16x8, f64, f32x4, i64x2, i128 sext, i32 sext, i64 sext, f32, i16 uext, i64x2, i16 uext, i32x4, i8 sext, i8x16, i8x16) -> i128 sext, i16x8, f64, f32x4, i16 uext, i128, i8 uext, i8 sext, f32x4, i8 sext, i64 sext, i8 sext, i8 uext, i32 sext, i8, i8 sext system_v { sig0 = (f32) -> f32 system_v sig1 = (f64) -> f64 system_v sig2 = (f32) -> f32 system_v sig3 = (f64) -> f64 system_v sig4 = (f32) -> f32 system_v sig5 = (f64) -> f64 system_v fn0 = %CeilF32 sig0 fn1 = %CeilF64 sig1 fn2 = %FloorF32 sig2 fn3 = %FloorF64 sig3 fn4 = %TruncF32 sig4 fn5 = %TruncF64 sig5 block0(v0: i32x4, v1: i16x8, v2: f64, v3: f32x4, v4: i64x2, v5: i128, v6: i32, v7: i64, v8: f32, v9: i16, v10: i64x2, v11: i16, v12: i32x4, v13: i8, v14: i8x16, v15: i8x16): v195 -> v6 v140 -> v7 v182 -> v7 v244 -> v7 v223 -> v8 v241 -> v10 v208 -> v11 v272 -> v12 v227 -> v13 v240 -> v13 v236 -> v14 v231 -> v15 v94 = iconst.i8 0 v95 = iconst.i16 0 v96 = iconst.i32 0 v97 = iconst.i64 0 v98 = uextend.i128 v97 ; v97 = 0 v99 = rotr v9, v7 v100 = rotr v99, v7 v101 = rotr v100, v7 v102 = rotr v101, v7 v103 = rotr v102, v7 v104 = rotr v103, v7 v105 = rotr v104, v7 v106 = rotr v105, v7 v107 = rotr v106, v7 v108 = rotr v107, v7 v109 = rotr v108, v7 v110 = rotr v109, v7 v111 = rotr v110, v7 v112 = rotr v111, v7 v113 = rotr v112, v7 v114 = rotr v113, v7 v115 = rotr v11, v7 v116 = rotr v115, v7 v117 = rotr v116, v7 v118 = rotr v117, v7 v119 = rotr v118, v7 v120 = rotr v119, v7 v121 = rotr v120, v7 v122 = rotr v121, v7 v123 = rotr v122, v7 v124 = rotr v123, v7 v125 = rotr v124, v7 v126 = rotr v125, v7 v127 = rotr v126, v7 v128 = rotr v127, v7 v129 = rotr v128, v7 v130 = rotr v129, v7 v131 = rotr v130, v7 v132 = rotr v131, v7 v133 = rotr v132, v7 v134 = rotr v133, v7 v135 = rotr v134, v7 v136 = rotr v135, v7 v137 = rotr v136, v7 v138 = rotr v137, v7 v139 -> v138 jump block1(v4, v0, v1, v5, v2, v0, v0, v0, v0, v0, v0, v0, v0, v0, v3, v0) block1(v16: i64x2, v17: i32x4, v18: i16x8, v19: i128, v20: f64, v21: i32x4, v22: i32x4, v23: i32x4, v24: i32x4, v25: i32x4, v26: i32x4, v27: i32x4, v28: i32x4, v29: i32x4, v30: f32x4, v31: i32x4): v259 -> v18 v242 -> v19 v273 -> v30 v141 = rotr.i16 v139, v140 v142 = rotr v141, v140 v143 = rotr v142, v140 v144 = rotr v143, v140 v145 = rotr v144, v140 v146 = rotr v145, v140 v147 = rotr v146, v140 v148 = rotr v147, v140 v149 = rotr v148, v140 v150 = rotr v149, v140 v151 = rotr v150, v140 v152 = rotr v151, v140 v153 = rotr v152, v140 v154 = rotr v153, v140 v155 = rotr v154, v140 v156 = rotr v155, v140 v157 = rotr v156, v140 v158 = rotr v157, v140 v159 = rotr v158, v140 v160 = rotr v159, v140 v161 = rotr v160, v140 v162 = rotr v161, v140 v163 = rotr v162, v140 v164 = rotr v163, v140 v165 = select v164, v16, v16 v197 -> v165 v166 = rotr v164, v140 v167 = rotr v166, v140 v168 = rotr v167, v140 v169 = rotr v168, v140 v170 = rotr v169, v140 v171 = rotr v170, v140 v172 = rotr v171, v140 v173 = rotr v172, v140 v174 = rotr v173, v140 v175 = rotr v174, v140 v176 = rotr v175, v140 v177 = rotr v176, v140 v178 = rotr v177, v140 v179 = rotr v178, v140 v180 = rotr v179, v140 v181 -> v180 jump block2(v20, v20, v20, v20, v20, v20, v20, v20, v20, v20) block2(v32: f64, v33: f64, v34: f64, v35: f64, v36: f64, v37: f64, v38: f64, v39: f64, v40: f64, v41: f64): v183 = rotr.i16 v181, v182 v184 = rotr v183, v182 v185 = rotr v184, v182 v186 = rotr v185, v182 v187 = rotr v186, v182 v188 = rotr v187, v182 v189 = rotr v188, v182 v190 = rotr v189, v182 v191 = rotr v190, v182 v192 = rotr v191, v182 v193 = rotr v192, v182 v194 = rotr v193, v182 v196 = bor_not.i32 v195, v195 v510 -> v196 v532 -> v196 v533 -> v196 v544 -> v196 v198 = isub.i64x2 v197, v197 v255 -> v198 v199 = rotr v194, v182 v200 = rotr v199, v182 v201 = rotr v200, v182 v202 = rotr v201, v182 v203 = rotr v202, v182 v204 = rotr v203, v182 v205 = rotr v204, v182 v206 = rotr v205, v182 v207 = rotr v206, v182 v209 = select_spectre_guard.i16 v196, v208, v208 v210 = select_spectre_guard v196, v209, v209 v211 = select_spectre_guard v196, v210, v210 v212 = select_spectre_guard v196, v211, v211 v213 = select_spectre_guard v196, v212, v212 v214 = select_spectre_guard v196, v213, v213 v215 = select_spectre_guard v196, v214, v214 v216 = select_spectre_guard v196, v215, v215 v217 = select_spectre_guard v196, v216, v216 v218 = select_spectre_guard v196, v217, v217 v219 = select_spectre_guard v196, v218, v218 v220 = select_spectre_guard v196, v219, v219 v221 = select_spectre_guard v196, v220, v220 v222 = select_spectre_guard v196, v221, v221 v224 = call fn0(v223) v261 -> v224 v225 = sshr v222, v222 v226 = sshr v225, v225 brif.i8 v227, block3(v41, v41, v225, v41, v41, v41, v41, v41, v41, v41), block6(v224, v182, v18, v226, v227, v225, v198, v19, v41, v30) block3(v42: f64, v43: f64, v44: i16, v45: f64, v46: f64, v47: f64, v48: f64, v49: f64, v50: f64, v51: f64): v228 = sshr v44, v44 v229 = sshr v228, v228 v230 = sshr v229, v229 v274 -> v230 v232 = band_not.i8x16 v231, v231 v233 = band_not v232, v232 v234 = band_not v233, v233 v235 = band_not v234, v234 v237 = band_not.i8x16 v236, v236 v238 = band_not v237, v237 v239 = band_not v238, v238 jump block4(v51, v51, v51, v240, v240, v241, v230, v239, v239, v239) block4(v52: f64, v53: f64, v54: f64, v55: i8, v56: i8, v57: i64x2, v58: i16, v59: i8x16, v60: i8x16, v61: i8x16): v243 = bmask.i8 v242 v245 = select_spectre_guard v244, v58, v58 v246 = bmask.i8 v242 v247 = bmask.i8 v242 v248 = bmask.i8 v242 v249 = bmask.i8 v242 v250 = uextend.i128 v245 v251 = band_not v54, v54 v252 = band_not v251, v251 v253 = band_not v252, v252 v254 = band_not v253, v253 v256 = sshr.i64x2 v255, v244 v257 = band_not v254, v254 v258 = band_not v257, v257 v260 = vany_true.i16x8 v259 v262 = func_addr.i64 fn0 v263 = call_indirect sig0, v262(v261) v264 = select v244, v57, v256 v265 = func_addr.i64 fn0 v266 = call_indirect sig0, v265(v263) v267 = select v244, v264, v256 v268 = func_addr.i64 fn0 v269 = call_indirect sig0, v268(v266) v275 -> v269 v270 = select v244, v267, v256 v545 = fcmp ne v258, v258 v546 = f64const -0x1.0000000000000p0 v547 = f64const 0x1.0000000000000p64 v548 = fcmp le v258, v546 ; v546 = -0x1.0000000000000p0 v549 = fcmp ge v258, v547 ; v547 = 0x1.0000000000000p64 v550 = bor v548, v549 v551 = bor v545, v550 v552 = f64const 0x1.0000000000000p0 v553 = select v551, v552, v258 ; v552 = 0x1.0000000000000p0 v271 = fcvt_to_uint.i64 v553 jump block5(v60, v61, v60, v61, v272, v273, v273, v256, v259, v259, v259, v259, v259, v274, v259, v250) block5(v62: i8x16, v63: i8x16, v64: i8x16, v65: i8x16, v66: i32x4, v67: f32x4, v68: f32x4, v69: i64x2, v70: i16x8, v71: i16x8, v72: i16x8, v73: i16x8, v74: i16x8, v75: i16, v76: i16x8, v77: i128): v276 = func_addr.i64 fn0 v277 = call_indirect sig0, v276(v275) v278 = iconst.i64 0x00fa_0000_7300_0092 v279 = iconst.i64 0x3138_3835_3404_0402 v280 = iconcat v278, v279 ; v278 = 0x00fa_0000_7300_0092, v279 = 0x3138_3835_3404_0402 v281 = icmp uge v77, v280 brif v281, block11, block10 block11: v282 = iconst.i64 0x0100_0000_003e_0100 v283 = iconst.i64 -7451204483956080384 v284 = iconcat v282, v283 ; v282 = 0x0100_0000_003e_0100, v283 = -7451204483956080384 v285 = icmp.i128 uge v77, v284 brif v285, block13, block12 block13: v286 = iconst.i64 -3617009525824946176 v287 = iconst.i64 -3617008641903833820 v288 = iconcat v286, v287 ; v286 = -3617009525824946176, v287 = -3617008641903833820 v289 = icmp.i128 uge v77, v288 brif v289, block15, block14 block15: v290 = iconst.i64 0x0707_0707_0707_0707 v291 = iconst.i64 -2232933263481567481 v292 = iconcat v290, v291 ; v290 = 0x0707_0707_0707_0707, v291 = -2232933263481567481 v293 = icmp.i128 uge v77, v292 brif v293, block17, block16 block17: v294 = iconst.i64 -2170205185142300191 v295 = iconst.i64 -2173864359839538719 v296 = iconcat v294, v295 ; v294 = -2170205185142300191, v295 = -2173864359839538719 v297 = icmp.i128 eq v77, v296 brif v297, block8(v277, v260, v274, v76, v256, v77, v258, v68, v271), block18 block18: v298 = iconst.i64 0x0707_0707_0707_0707 v299 = iconst.i64 -2232933263481567481 v300 = iconcat v298, v299 ; v298 = 0x0707_0707_0707_0707, v299 = -2232933263481567481 v301 = icmp.i128 eq v77, v300 brif v301, block8(v277, v260, v274, v76, v256, v77, v258, v68, v271), block6(v277, v271, v76, v75, v260, v274, v256, v77, v258, v68) block16: v302 = iconst.i64 -3617008643992366767 v303 = iconst.i64 -3616973457531744819 v304 = iconcat v302, v303 ; v302 = -3 [message truncated]
Last updated: Apr 12 2026 at 23:10 UTC