Wasmtime GitHub notifications bot (May 04 2022 at 19:55): Wasmtime GitHub notifications bot (May 04 2022 at 19:55):cfallin commented on issue #1154:
This is all covered now in the current
x64backend, and we have VEX encodings for many vector instructions -- closing now!
Wasmtime GitHub notifications bot (May 04 2022 at 19:55):cfallin closed issue #1154:
- What is the feature or code improvement you would like to do in Cranelift?
Add VEX and EVEX encoding mechanisms for x86 code generation.
- What is the value of adding this in Cranelift?
Certain Wasm SIMD operations (e.g. convert, trunc) only can be lowered with VEX and EVEX encodings. Many VEX and EVEX encodings are only available in later SIMD feature sets (e.g. AVX-512); adding the ability to use VEX and EVEX encodings does not preclude legalizations for x86 CPUs without later SIMD feature sets, but that is a separate issue.
- Do you have an implementation plan, and/or ideas for data structures or algorithms to use?
I think the relevant thing here is that it may impact how we go about resolving bytecodealliance/wasmtime#1141.
- Have you considered alternative implementations? If so, how are they better or worse than your proposal?
Not having the ability to use VEX and EVEX encodings would force cranelift to use multi-instruction legalizations instead of optimal instructions during instruction selection.
Last updated: Oct 23 2024 at 20:03 UTC