Stream: git-wasmtime

Topic: wasmtime / issue #1140 Figure out a better type during `b...

Wasmtime GitHub notifications bot (May 04 2022 at 23:09):

cfallin commented on issue #1140:

Is this still a relevant issue with the new backends @abrown?

Wasmtime GitHub notifications bot (May 04 2022 at 23:12):

abrown commented on issue #1140:

Nope, closing.

Wasmtime GitHub notifications bot (May 04 2022 at 23:12):

abrown closed issue #1140:

As noted in https://github.com/CraneStation/cranelift/pull/1120#discussion_r335156013, when moving a scalar value (I32 or I64) to a vector register in x86, the destination must be a a I64x2 due to typing restrictions that ensure vectors have more than one lane. This may be rather confusing when looking at CLIF IR because the intent of that move (using the bitcast instruction) is to zero out the upper bits and only load the lower bits using the scalar value--it's more a I128x1 than anything else.

There are several options here, some of which are:

• leave as-is with I64x2 and remove the TODO comment
• change the typing restrictions to allow I128x1
• use a different CLIF instruction altogether
• etc.

Last updated: Dec 23 2024 at 12:05 UTC