cfallin commented on issue #1139:
Thanks for the links! IMHO the instruction scheduling that this paper and presentation describes is more important for smaller, in-order cores, and less for modern out-of-order cores, even small ones. Most of our users (certainly not all!) are on OoO cores. Furthermore incorporating instruction scheduling would be quite a significant overhaul in our current lowering approach. I'm open to thinking more about this if someone wants to propose a way to integrate this into our current framework, though; in the meantime I think we can go ahead and close this issue.
cfallin closed issue #1139:
ACO is a compiler written by Valve as a replacement for LLVM in MESA to compile shaders when using amd gpu's. Both compilation speed and execution speed of shaders are very important for games. The former design constraint aligns with Cranelift's goal, while the later is nice to have. It also uses a single IR, like Cranelift.
https://xdc2019.x.org/event/5/contributions/334/attachments/431/683/ACO_XDC2019.pdf
At https://github.com/mesa3d/mesa/blob/93c8ebfa780ebd1495095e794731881aef29e7d3/src/amd/compiler/aco_spill.cpp#L32 a paper called "Register Spilling and Live-Range Splitting for SSA-Form Programs" is referenced.
At https://github.com/mesa3d/mesa/blob/2ea9e59e8d976ec77800d2a20645087b96d1e241/src/amd/compiler/aco_scheduler.cpp#L50 a paper called "A Novel Lightweight Instruction Scheduling Algorithm for Just-In-Time Compiler" is referenced. (Unfortunately behind a paywall)
Last updated: Dec 23 2024 at 12:05 UTC