cfallin labeled issue #1077:
Some architectures make use of branch delay slots, such as MIPS and SPARC; some even more exotic ones have load delay slots as well. Often enough there are also instructions with results only usable after certain number of cycles.
I'm trying to port Cranelift to MIPS64. I glanced over the codebase and found no support for filling the delay slots; I had to emit NOPs after every branch in the meantime. (Indeed I didn't expect any because all currently supported architectures have no delay slots.)
So what's the current plan regarding this? A roadmap or implementation guide would be great!
cfallin labeled issue #1077:
Some architectures make use of branch delay slots, such as MIPS and SPARC; some even more exotic ones have load delay slots as well. Often enough there are also instructions with results only usable after certain number of cycles.
I'm trying to port Cranelift to MIPS64. I glanced over the codebase and found no support for filling the delay slots; I had to emit NOPs after every branch in the meantime. (Indeed I didn't expect any because all currently supported architectures have no delay slots.)
So what's the current plan regarding this? A roadmap or implementation guide would be great!
fitzgen closed issue #1077:
Some architectures make use of branch delay slots, such as MIPS and SPARC; some even more exotic ones have load delay slots as well. Often enough there are also instructions with results only usable after certain number of cycles.
I'm trying to port Cranelift to MIPS64. I glanced over the codebase and found no support for filling the delay slots; I had to emit NOPs after every branch in the meantime. (Indeed I didn't expect any because all currently supported architectures have no delay slots.)
So what's the current plan regarding this? A roadmap or implementation guide would be great!
fitzgen commented on issue #1077:
Chris gave an answer for what we could do if we ever need this in a particular backend (like mips), but we won't add these semantics to CLIF itself.
Last updated: Jan 10 2026 at 20:04 UTC