cfallin labeled issue #1067:
This would add two new instructions to cranelift,
bextrandbmak. They provide a easy to optimize, and easy to generate mechanism for bitfield manipulation.bextr
a = bextr target, size, offsetbextr will extract a _n_ bit large field at the provided offset, and return it in
a, shifted so that the LSB of the field is also the LSB ofa.
a's type is inferred fromtargetVisual example
offset = 4 size = 4 typeof target = i8 xxxx **** \__/----V 0000 xxxxbmak
a = bmak target, size, offsetbmak will fill a _n_ bit large field at the provided offset with 1s, the rest with 0. The generated field will then be applied to
targetusing a bitwise AND, and the result will be returned ina.
a's type is inferred fromtarget
bmak is designed so that you can simply use a bitwise or to combine the fields.Visual Example
offset = 2 size = 4 typeof target = i8 xx0101xx \__/ / \ 00010100
cfallin labeled issue #1067:
This would add two new instructions to cranelift,
bextrandbmak. They provide a easy to optimize, and easy to generate mechanism for bitfield manipulation.bextr
a = bextr target, size, offsetbextr will extract a _n_ bit large field at the provided offset, and return it in
a, shifted so that the LSB of the field is also the LSB ofa.
a's type is inferred fromtargetVisual example
offset = 4 size = 4 typeof target = i8 xxxx **** \__/----V 0000 xxxxbmak
a = bmak target, size, offsetbmak will fill a _n_ bit large field at the provided offset with 1s, the rest with 0. The generated field will then be applied to
targetusing a bitwise AND, and the result will be returned ina.
a's type is inferred fromtarget
bmak is designed so that you can simply use a bitwise or to combine the fields.Visual Example
offset = 2 size = 4 typeof target = i8 xx0101xx \__/ / \ 00010100
cfallin commented on issue #1067:
We discussed this during old-issue triage today and agreed that it is probably better to have users implement this behavior with shifts/masks and then pattern-match that during isel if a particular target ISA has a nice instruction for it. This fits better with the general trend of making CLIF a simple core IR, especially as not every ISA has such instructions -- this would have to be re-expanded in backends otherwise, and only after the point that that expansion could be optimized. I'll close this issue but thank you for the discussion!
cfallin closed issue #1067:
This would add two new instructions to cranelift,
bextrandbmak. They provide a easy to optimize, and easy to generate mechanism for bitfield manipulation.bextr
a = bextr target, size, offsetbextr will extract a _n_ bit large field at the provided offset, and return it in
a, shifted so that the LSB of the field is also the LSB ofa.
a's type is inferred fromtargetVisual example
offset = 4 size = 4 typeof target = i8 xxxx **** \__/----V 0000 xxxxbmak
a = bmak target, size, offsetbmak will fill a _n_ bit large field at the provided offset with 1s, the rest with 0. The generated field will then be applied to
targetusing a bitwise AND, and the result will be returned ina.
a's type is inferred fromtarget
bmak is designed so that you can simply use a bitwise or to combine the fields.Visual Example
offset = 2 size = 4 typeof target = i8 xx0101xx \__/ / \ 00010100
moonheart08 commented on issue #1067:
We discussed this during old-issue triage today and agreed that it is probably better to have users implement this behavior with shifts/masks and then pattern-match that during isel if a particular target ISA has a nice instruction for it. This fits better with the general trend of making CLIF a simple core IR, especially as not every ISA has such instructions -- this would have to be re-expanded in backends otherwise, and only after the point that that expansion could be optimized. I'll close this issue but thank you for the discussion!
7 years later with a stronger understanding of compilers and architectures, and I agree this is probably the right approach. Yet another issue I didn't remember creating resolved today!
Rafferty97 commented on issue #1067:
Hi, I'm writing a compiler that does a lot of bit manipulation, and using cranelift for the backend.
I've noticed that quite a few instances where two instructions could be compressed into a single UBFM or SBFM instruction.
I'd be willing to open a PR that adds the appropriate ISLE rules, if it's likely to be merged?
cfallin commented on issue #1067:
@Rafferty97 yes, PRs that improve instruction selection are always welcome!
Rafferty97 commented on issue #1067:
@Rafferty97 yes, PRs that improve instruction selection are always welcome!
Awesome, thanks for the quick response! I'll work on it now and put up a PR when I can. Should I file a GitHub issue too or is a detailed PR sufficient?
cfallin commented on issue #1067:
A PR is fine, with a reasonable description and ideally a test showing the new lowering -- no need to file a specific issue beforehand.
Rafferty97 commented on issue #1067:
Hey @cfallin, it was more effort than I anticipated, but I finally got a PR up :)
Last updated: Aug 30 2026 at 09:07 UTC