Stream: git-wasmtime

Topic: wasmtime / issue #10585 Cranelift: try_call regalloc veri...

Wasmtime GitHub notifications bot (Apr 15 2025 at 15:07):

bjorn3 added the cranelift label to Issue #10585.

Wasmtime GitHub notifications bot (Apr 15 2025 at 15:07):

bjorn3 added the bug label to Issue #10585.

Wasmtime GitHub notifications bot (Apr 15 2025 at 15:07):

bjorn3 opened issue #10585:

Thanks for filing an issue! Please fill out the TODOs below.

.clif Test Case

test compile
set regalloc_checker=1
target x86_64
target aarch64

function u0:0() -> i32 tail {
    sig0 = () -> i32 tail
    fn0 = u0:1 sig0

block0:
    try_call fn0(), sig0, block1(ret0), []

block1(v0: i32):
    return v0
}

Steps to Reproduce

• cargo run -- test crash.clif

Expected Results

Compiles

Actual Results

 ERROR cranelift_codegen::machinst::compile > Register allocation checker errors:
CheckerErrors { errors: [UnknownValueInAllocation { inst: Inst(2), op: Use: v195i fixed(p0i), alloc: p0i }] }
for vcode:
VCode {
  Entry block: 0
Block 0([]):
    (original IR block: block0)
    (successor: Block 1([VReg(vreg = 196, class = Int)]))
  Inst 0: load_ext_name userextname0+0, %v197
  Inst 1: call    *%v197; jmp MachLabel(1); catch []
Block 1([VReg(vreg = 195, class = Int)]):
    (original IR block: block1)
  Inst 2: rets %v195=%rax
}

Versions and Environment

Cranelift version or commit: d69ef83e813c9d49ae98796480a6c829d5fdc5bf (current main)

Operating system: N/A

Architecture: x86_64 and arm64

Wasmtime GitHub notifications bot (Apr 15 2025 at 15:07):

bjorn3 edited issue #10585:

.clif Test Case

test compile
set regalloc_checker=1
target x86_64
target aarch64

function u0:0() -> i32 tail {
    sig0 = () -> i32 tail
    fn0 = u0:1 sig0

block0:
    try_call fn0(), sig0, block1(ret0), []

block1(v0: i32):
    return v0
}

Steps to Reproduce

• cargo run -- test crash.clif

Expected Results

Compiles

Actual Results

 ERROR cranelift_codegen::machinst::compile > Register allocation checker errors:
CheckerErrors { errors: [UnknownValueInAllocation { inst: Inst(2), op: Use: v195i fixed(p0i), alloc: p0i }] }
for vcode:
VCode {
  Entry block: 0
Block 0([]):
    (original IR block: block0)
    (successor: Block 1([VReg(vreg = 196, class = Int)]))
  Inst 0: load_ext_name userextname0+0, %v197
  Inst 1: call    *%v197; jmp MachLabel(1); catch []
Block 1([VReg(vreg = 195, class = Int)]):
    (original IR block: block1)
  Inst 2: rets %v195=%rax
}

Versions and Environment

Cranelift version or commit: d69ef83e813c9d49ae98796480a6c829d5fdc5bf (current main)

Operating system: N/A

Architecture: x86_64 and arm64

Wasmtime GitHub notifications bot (Apr 15 2025 at 15:48):

cfallin commented on issue #10585:

Taking a look!

Wasmtime GitHub notifications bot (Apr 15 2025 at 16:48):

cfallin commented on issue #10585:

Addressed by bytecodealliance/regalloc#224 (and then a release and an update here). The checker basically wasn't considering uses/defs/clobbers on branches but try-calls make this newly relevant. Thanks for the report!

Wasmtime GitHub notifications bot (Apr 15 2025 at 16:48):

cfallin edited a comment on issue #10585:

Addressed by bytecodealliance/regalloc2#224 (and then a release and an update here). The checker basically wasn't considering uses/defs/clobbers on branches but try-calls make this newly relevant. Thanks for the report!

Wasmtime GitHub notifications bot (Apr 15 2025 at 21:13):

cfallin closed issue #10585:

.clif Test Case

test compile
set regalloc_checker=1
target x86_64
target aarch64

function u0:0() -> i32 tail {
    sig0 = () -> i32 tail
    fn0 = u0:1 sig0

block0:
    try_call fn0(), sig0, block1(ret0), []

block1(v0: i32):
    return v0
}

Steps to Reproduce

• cargo run -- test crash.clif

Expected Results

Compiles

Actual Results

 ERROR cranelift_codegen::machinst::compile > Register allocation checker errors:
CheckerErrors { errors: [UnknownValueInAllocation { inst: Inst(2), op: Use: v195i fixed(p0i), alloc: p0i }] }
for vcode:
VCode {
  Entry block: 0
Block 0([]):
    (original IR block: block0)
    (successor: Block 1([VReg(vreg = 196, class = Int)]))
  Inst 0: load_ext_name userextname0+0, %v197
  Inst 1: call    *%v197; jmp MachLabel(1); catch []
Block 1([VReg(vreg = 195, class = Int)]):
    (original IR block: block1)
  Inst 2: rets %v195=%rax
}

Versions and Environment

Cranelift version or commit: d69ef83e813c9d49ae98796480a6c829d5fdc5bf (current main)

Operating system: N/A

Architecture: x86_64 and arm64

Last updated: Dec 06 2025 at 06:05 UTC