Stream: git-wasmtime

Topic: wasmtime / issue #10572 [DI] Zeroing of locals combined w...

view this post on Zulip Wasmtime GitHub notifications bot (Apr 13 2025 at 17:33):

SingleAccretion opened issue #10572:

Reproduction:
1) Set $env:WASMTIME_LOG="cranelift_codegen=trace".
2) Run wasmtime.exe compile -Ddebug-info -Oopt-level=2 -Ccache=n -Cparallel-compilation=n tests\all\debug\testsuite\fib-wasm.wasm.
3) Observe the VL table, it should look something like this:

|BB|Inst    |IP  |VL0     |VL1     |VL3     |VL6     |VL7     |VL8     |VL9     |VL13    |VL14    |VL15    |VL21    |VL4294967294|
|--|--------|----|--------|--------|--------|--------|--------|--------|--------|--------|--------|--------|--------|------------|
|B0|Inst 0  |4   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |       |
|  |Inst 1  |7   |v194|p6i|    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |v192|p7i    |
|  |Inst 2  |10  |*   |p6i|v243|p0i|    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |*   |p7i    |
|  |Inst 3  |14  |*   |p6i|*   |p0i|    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |*   |p7i    |
|  |Inst 4  |17  |*   |p6i|*   |   |v241|p0i|    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |*   |p7i    |
|  |Inst 5  |21  |*   |p6i|*   |   |*   |p0i|    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |*   |p7i    |
|  |Inst 6  |25  |*   |   |v203|   |v203|   |v203|   |v203|   |v203|   |v203|   |v203|   |v203|   |v203|   |v203|   |*   |p7i    |
|  |Inst 7  |33  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|  |Inst 8  |41  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|  |Inst 9  |49  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|B1|Inst 10 |49  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|  |Inst 11 |53  |*   |   |*   |   |*   |   |v239|p6i|*   |   |v239|p6i|*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|  |Inst 12 |57  |*   |   |*   |   |*   |   |*   |p6i|v238|p1i|*   |p6i|v238|p1i|*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|  |Inst 13 |59  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|B2|Inst 14 |65  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|  |Inst 15 |69  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |v237|p1i|*   |   |*   |   |*   |   |*   |p7i    |
|  |Inst 16 |73  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|  |Inst 17 |77  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |v236|p1i|*   |   |*   |   |*   |p7i    |
|  |Inst 18 |81  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|  |Inst 19 |86  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |v235|p8i|*   |   |*   |p7i    |
|  |Inst 20 |91  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|  |Inst 21 |97  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|  |Inst 22 |102 |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|B3|Inst 23 |107 |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|  |Inst 24 |111 |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |v233|p0i|*   |p7i    |
|  |Inst 25 |111 |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p0i|*   |       |

Notice the suspicious Inst 6 row, where, seemingly, all the various lifetimes get abruptly cut off.

This is because earlier the zeroing instruction (inst0) inserted by WASM translation to honor the WASM semantic of zeroed locals in entry, is moved closer to its first use, and then this happens:

lower_clif_block: block block0 inst inst17 (Binary { opcode: Iadd, args: [v13, v19] }) is_branch false side_effect false value_needed false
value labeling: srcloc @+0028: inst inst17
get_value_labels: val v20 -> None
lower_clif_block: block block0 inst inst16 (UnaryImm { opcode: Iconst, imm: Imm64(20) }) is_branch false side_effect false value_needed false
value labeling: srcloc @+0028: inst inst16
get_value_labels: val v19 -> None
lower_clif_block: block block0 inst inst0 (UnaryImm { opcode: Iconst, imm: Imm64(0) }) is_branch false side_effect false value_needed false
value labeling: srcloc @+0000: inst inst0
get_value_labels: val v4 -> Some(Starts([ValueLabelStart { from: RelSourceLoc(0), label: VL1 }, ValueLabelStart { from: RelSourceLoc(0), label: VL2 }, ValueLabelStart { from: RelSourceLoc(0), label: VL3 }, ValueLabelStart { from: RelSourceLoc(0), label: VL4 }, ValueLabelStart { from: RelSourceLoc(0), label: VL5 }, ValueLabelStart { from: RelSourceLoc(0), label: VL6 }, ValueLabelStart { from: RelSourceLoc(0), label: VL7 }, ValueLabelStart { from: RelSourceLoc(0), label: VL8 }, ValueLabelStart { from: RelSourceLoc(0), label: VL9 }, ValueLabelStart { from: RelSourceLoc(0), label: VL10 }, ValueLabelStart { from: RelSourceLoc(0), label: VL11 }, ValueLabelStart { from: RelSourceLoc(0), label: VL12 }, ValueLabelStart { from: RelSourceLoc(0), label: VL13 }, ValueLabelStart { from: RelSourceLoc(0), label: VL14 }, ValueLabelStart { from: RelSourceLoc(0), label: VL15 }, ValueLabelStart { from: RelSourceLoc(0), label: VL16 }, ValueLabelStart { from: RelSourceLoc(0), label: VL17 }, ValueLabelStart { from: RelSourceLoc(0), label: VL18 }, ValueLabelStart { from: RelSourceLoc(0), label: VL19 }, ValueLabelStart { from: RelSourceLoc(0), label: VL20 }, ValueLabelStart { from: RelSourceLoc(0), label: VL21 }]))
value labeling: defines val v4 -> reg v203 -> label VL11
value labeling: defines val v4 -> reg v203 -> label VL3
value labeling: defines val v4 -> reg v203 -> label VL14
value labeling: defines val v4 -> reg v203 -> label VL6
value labeling: defines val v4 -> reg v203 -> label VL17
value labeling: defines val v4 -> reg v203 -> label VL9
value labeling: defines val v4 -> reg v203 -> label VL20
value labeling: defines val v4 -> reg v203 -> label VL1
value labeling: defines val v4 -> reg v203 -> label VL12
value labeling: defines val v4 -> reg v203 -> label VL4
value labeling: defines val v4 -> reg v203 -> label VL15
value labeling: defines val v4 -> reg v203 -> label VL7
value labeling: defines val v4 -> reg v203 -> label VL18
value labeling: defines val v4 -> reg v203 -> label VL10
value labeling: defines val v4 -> reg v203 -> label VL21
value labeling: defines val v4 -> reg v203 -> label VL2
value labeling: defines val v4 -> reg v203 -> label VL13
value labeling: defines val v4 -> reg v203 -> label VL5
value labeling: defines val v4 -> reg v203 -> label VL16
value labeling: defines val v4 -> reg v203 -> label VL8
value labeling: defines val v4 -> reg v203 -> label VL19
lower_clif_block: block block0 inst inst12 (Store { opcode: Store, args: [v2, v15], flags: MemFlags { bits: 32420 }, offset: Offset32(0) }) is_branch false side_effect true value_needed false

view this post on Zulip Wasmtime GitHub notifications bot (Apr 15 2025 at 16:48):

SingleAccretion edited issue #10572:

Reproduction:
1) Set $env:WASMTIME_LOG="cranelift_codegen=trace".
2) Run wasmtime.exe compile -Ddebug-info -Oopt-level=2 -Ccache=n -Cparallel-compilation=n tests\all\debug\testsuite\fib-wasm.wasm.
3) Observe the VL table, it should look something like this:

|BB|Inst    |IP  |VL0     |VL1     |VL3     |VL6     |VL7     |VL8     |VL9     |VL13    |VL14    |VL15    |VL21    |VL4294967294|
|--|--------|----|--------|--------|--------|--------|--------|--------|--------|--------|--------|--------|--------|------------|
|B0|Inst 0  |4   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |       |
|  |Inst 1  |7   |v194|p6i|    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |v192|p7i    |
|  |Inst 2  |10  |*   |p6i|v243|p0i|    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |*   |p7i    |
|  |Inst 3  |14  |*   |p6i|*   |p0i|    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |*   |p7i    |
|  |Inst 4  |17  |*   |p6i|*   |   |v241|p0i|    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |*   |p7i    |
|  |Inst 5  |21  |*   |p6i|*   |   |*   |p0i|    |   |    |   |    |   |    |   |    |   |    |   |    |   |    |   |*   |p7i    |
|  |Inst 6  |25  |*   |   |v203|   |v203|   |v203|   |v203|   |v203|   |v203|   |v203|   |v203|   |v203|   |v203|   |*   |p7i    |
|  |Inst 7  |33  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|  |Inst 8  |41  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|  |Inst 9  |49  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|B1|Inst 10 |49  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|  |Inst 11 |53  |*   |   |*   |   |*   |   |v239|p6i|*   |   |v239|p6i|*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|  |Inst 12 |57  |*   |   |*   |   |*   |   |*   |p6i|v238|p1i|*   |p6i|v238|p1i|*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|  |Inst 13 |59  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|B2|Inst 14 |65  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|  |Inst 15 |69  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |v237|p1i|*   |   |*   |   |*   |   |*   |p7i    |
|  |Inst 16 |73  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|  |Inst 17 |77  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |v236|p1i|*   |   |*   |   |*   |p7i    |
|  |Inst 18 |81  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|  |Inst 19 |86  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |v235|p8i|*   |   |*   |p7i    |
|  |Inst 20 |91  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|  |Inst 21 |97  |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|  |Inst 22 |102 |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|B3|Inst 23 |107 |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p7i    |
|  |Inst 24 |111 |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |v233|p0i|*   |p7i    |
|  |Inst 25 |111 |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |   |*   |p0i|*   |       |

Notice the suspicious Inst 6 row, where, seemingly, all the various lifetimes get abruptly cut off.

This is because earlier the zeroing instruction (inst0) inserted by WASM translation to honor the WASM semantic of zeroed locals at entry, is moved closer to its first use, and then this happens:

lower_clif_block: block block0 inst inst17 (Binary { opcode: Iadd, args: [v13, v19] }) is_branch false side_effect false value_needed false
value labeling: srcloc @+0028: inst inst17
get_value_labels: val v20 -> None
lower_clif_block: block block0 inst inst16 (UnaryImm { opcode: Iconst, imm: Imm64(20) }) is_branch false side_effect false value_needed false
value labeling: srcloc @+0028: inst inst16
get_value_labels: val v19 -> None
lower_clif_block: block block0 inst inst0 (UnaryImm { opcode: Iconst, imm: Imm64(0) }) is_branch false side_effect false value_needed false
value labeling: srcloc @+0000: inst inst0
get_value_labels: val v4 -> Some(Starts([ValueLabelStart { from: RelSourceLoc(0), label: VL1 }, ValueLabelStart { from: RelSourceLoc(0), label: VL2 }, ValueLabelStart { from: RelSourceLoc(0), label: VL3 }, ValueLabelStart { from: RelSourceLoc(0), label: VL4 }, ValueLabelStart { from: RelSourceLoc(0), label: VL5 }, ValueLabelStart { from: RelSourceLoc(0), label: VL6 }, ValueLabelStart { from: RelSourceLoc(0), label: VL7 }, ValueLabelStart { from: RelSourceLoc(0), label: VL8 }, ValueLabelStart { from: RelSourceLoc(0), label: VL9 }, ValueLabelStart { from: RelSourceLoc(0), label: VL10 }, ValueLabelStart { from: RelSourceLoc(0), label: VL11 }, ValueLabelStart { from: RelSourceLoc(0), label: VL12 }, ValueLabelStart { from: RelSourceLoc(0), label: VL13 }, ValueLabelStart { from: RelSourceLoc(0), label: VL14 }, ValueLabelStart { from: RelSourceLoc(0), label: VL15 }, ValueLabelStart { from: RelSourceLoc(0), label: VL16 }, ValueLabelStart { from: RelSourceLoc(0), label: VL17 }, ValueLabelStart { from: RelSourceLoc(0), label: VL18 }, ValueLabelStart { from: RelSourceLoc(0), label: VL19 }, ValueLabelStart { from: RelSourceLoc(0), label: VL20 }, ValueLabelStart { from: RelSourceLoc(0), label: VL21 }]))
value labeling: defines val v4 -> reg v203 -> label VL11
value labeling: defines val v4 -> reg v203 -> label VL3
value labeling: defines val v4 -> reg v203 -> label VL14
value labeling: defines val v4 -> reg v203 -> label VL6
value labeling: defines val v4 -> reg v203 -> label VL17
value labeling: defines val v4 -> reg v203 -> label VL9
value labeling: defines val v4 -> reg v203 -> label VL20
value labeling: defines val v4 -> reg v203 -> label VL1
value labeling: defines val v4 -> reg v203 -> label VL12
value labeling: defines val v4 -> reg v203 -> label VL4
value labeling: defines val v4 -> reg v203 -> label VL15
value labeling: defines val v4 -> reg v203 -> label VL7
value labeling: defines val v4 -> reg v203 -> label VL18
value labeling: defines val v4 -> reg v203 -> label VL10
value labeling: defines val v4 -> reg v203 -> label VL21
value labeling: defines val v4 -> reg v203 -> label VL2
value labeling: defines val v4 -> reg v203 -> label VL13
value labeling: defines val v4 -> reg v203 -> label VL5
value labeling: defines val v4 -> reg v203 -> label VL16
value labeling: defines val v4 -> reg v203 -> label VL8
value labeling: defines val v4 -> reg v203 -> label VL19
lower_clif_block: block block0 inst inst12 (Store { opcode: Store, args: [v2, v15], flags: MemFlags { bits: 32420 }, offset: Offset32(0) }) is_branch false side_effect true value_needed false

view this post on Zulip Wasmtime GitHub notifications bot (Apr 24 2025 at 16:14):

fitzgen added the cranelift:area:debug label to Issue #10572.

Last updated: Dec 06 2025 at 06:05 UTC