eagr opened PR #9912 from eagr:pulley-pairwise
to bytecodealliance:main
:
part of #9783
eagr requested wasmtime-compiler-reviewers for a review on PR #9912.
eagr requested fitzgen for a review on PR #9912.
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eagr updated PR #9912.
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alexcrichton submitted PR review.
alexcrichton created PR review comment:
For these instructions we'll definitely want to avoid an intermediate allocation of a
Vec
. It might be reasonable to just use manual indices here and/or "macro expanding" some code. I don't think the standard library helpers for all this are necessarily the best way to go.
Xuanwo submitted PR review.
Xuanwo created PR review comment:
We only have limited numbers of items to operate, maybe we can just write them out like:
fn vaddpairwisei16x8_s(&mut self, operands: BinaryOperands<VReg>) -> ControlFlow<Done> { let a = self.state[operands.src1].get_i16x8(); let b = self.state[operands.src2].get_i16x8(); let mut result = [0i16; 8]; // Process first 4 elements from a result[0] = a[0].wrapping_add(a[1]); result[1] = a[2].wrapping_add(a[3]); result[2] = a[4].wrapping_add(a[5]); result[3] = a[6].wrapping_add(a[7]); // Process first 4 elements from b result[4] = b[0].wrapping_add(b[1]); result[5] = b[2].wrapping_add(b[3]); result[6] = b[4].wrapping_add(b[5]); result[7] = b[6].wrapping_add(b[7]); self.state[operands.dst].set_i16x8(result); ControlFlow::Continue(()) }
Xuanwo edited PR review comment.
eagr submitted PR review.
eagr created PR review comment:
Guess I need a mind shift for this :)
eagr updated PR #9912.
eagr updated PR #9912.
alexcrichton submitted PR review.
eagr updated PR #9912.
alexcrichton merged PR #9912.
Last updated: Jan 24 2025 at 00:11 UTC