MarinPostma opened PR #9798 from MarinPostma:i32-div-aarch64
to bytecodealliance:main
:
This PR takes first steps towards completing #9766, by implementing support for 32bit unsigned division in cranelift and winch.
we had to take the following steps to enable that:
- extend the ISLE lowering rules in cranelift to properly handle 32bits udiv, by have a rule that matches 64bit division, and another for anything else that fits 32bit. The 32 bits basically is the old 64bits rule but for 32bits.
- stop extending registers to 64bits in the ISLE rules.
- patch the emit code to emit the correct instruction for 32bits division.
- in winch: stop emitting extend operations for urem and udiv.
question: we emit a
trapz
to catch overflow, but trapz currently only work with 64bits registers. We either need a new trapz instruction for 32bits, or, pass the type info to trapz during lower, for emission. This would cover the case where the lower half of the divisor is 0, but not the upper part. Although, is that even possible in practice, by code generated by cranelift?
MarinPostma requested cfallin for a review on PR #9798.
MarinPostma requested wasmtime-compiler-reviewers for a review on PR #9798.
MarinPostma requested alexcrichton for a review on PR #9798.
MarinPostma requested wasmtime-core-reviewers for a review on PR #9798.
MarinPostma updated PR #9798.
MarinPostma updated PR #9798.
github-actions[bot] commented on PR #9798:
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cc @saulecabrera
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MarinPostma updated PR #9798.
MarinPostma edited PR #9798:
This PR takes first steps towards completing #9766, by implementing support for 32bit unsigned division in cranelift and winch.
we had to take the following steps to enable that:
- extend the ISLE lowering rules in cranelift to properly handle 32bits udiv, by have a rule that matches 64bit division, and another for anything else that fits 32bit. The 32 bits basically is the old 64bits rule but for 32bits.
- stop extending registers to 64bits in the ISLE rules.
- patch the emit code to emit the correct instruction for 32bits division.
- in winch: stop emitting extend operations for urem and udiv.
- Make
trap_if
size aware: this avoids having to perform extensions beforecbz
, shaving more instructions.
MarinPostma updated PR #9798.
MarinPostma submitted PR review.
MarinPostma created PR review comment:
I think we mostly had two choices here:
- either make the size part of the
CondBrKind
, which is tighter, but yields more changes in the code- or setting the size in the op itself (current approach), which required less changes
MarinPostma edited PR #9798:
This PR takes first steps towards completing #9766, by implementing support for 32bit unsigned division in cranelift and winch.
we had to take the following steps to enable that:
- extend the ISLE lowering rules in cranelift to properly handle 32bits udiv, by have a rule that matches 64bit division, and another for anything else that fits 32bit. The 32 bits basically is the old 64bits rule but for 32bits.
- stop extending registers to 64bits in the ISLE rules.
- patch the emit code to emit the correct instruction for 32bits division.
- in winch: stop emitting extend operations for urem and udiv.
- Make
trap_if
size aware: this avoids having to perform extensions beforecbz
, shaving more instructions. This is reflected in the lowering rules for checking division by zero for udiv.
MarinPostma has marked PR #9798 as ready for review.
MarinPostma updated PR #9798.
cfallin submitted PR review:
Thanks! One thought below on the way that
TrapIf
is extended, but generally I like how this is turning out.
cfallin created PR review comment:
todo!()
here -- can we just show the reg (and below for vector too) withshow_reg
for now?
cfallin created PR review comment:
Also, separately, if we modify
CondBrKind
, this is toward the direction that we want for supporting 32-bit zero/nonzero tests in regular conditional branches too. We don't have to implement that now (you canunimplemented!()
it in theCondBr
case; but if you wanted to, it would certainly be fine with me) but it's nice to lay the groundwork.
cfallin created PR review comment:
I think I might prefer the first option actually -- I was a bit confused at first how the
OperandSize
would affect theTrapIf
if we're just talking about conditional branch kinds likeb.lo
,b.hi
, etc; until I realized thatCondBrKind::Zero(reg)
andNonZero(reg)
exist and encodecbz
/cbnz
. If you don't mind, do you think you could try the refactor out? On the upside, it seems like it should get rid of a bunch of extraneousOperandSize
s on branches emitted in various places that are condcode-based (e.g. inabi.rs
above and in many of the emit-tests below).
MarinPostma commented on PR #9798:
Thanks @cfallin, will do the refactor :+1:
MarinPostma submitted PR review.
MarinPostma created PR review comment:
This make sense to me, I'll refactor
MarinPostma updated PR #9798.
MarinPostma updated PR #9798.
github-actions[bot] commented on PR #9798:
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cc @cfallin, @fitzgen
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MarinPostma requested cfallin for a review on PR #9798.
cfallin submitted PR review:
Looks great; thanks a bunch!
cfallin merged PR #9798.
Last updated: Dec 23 2024 at 12:05 UTC