Wasmtime GitHub notifications bot (Aug 05 2024 at 15:21): Wasmtime GitHub notifications bot (Aug 05 2024 at 15:21):afonso360 opened PR #9079 from afonso360:riscv-stricter-isa-checking to bytecodealliance:main:
:wave: Hey,
The RISC-V ISA has a lot of extensions to support a lot of little things. One example of this, is that it does not support F32 types with the base ISA. To support that we need the F ISA extension.
The RISC-V backend mostly ignored these requirements since both F and D are part of the minimum ISA profile that we request (IMAFD). With this PR we now try to check for those flags when lowering F32 / F64 instructions. (This is fixed in the first commit)
Additionally on the vector side, we only ever checked the vector size, but not the supported types. This means that currently we can lower a F8x16 vector, but we never check that that type is supported by the target CPU. (This is fixed in the second commit)
This is a preparation commit for FP16 support, where we mostly just have to check for a ISA flag to support it. With this change we can now do that in a single place.
Wasmtime GitHub notifications bot (Aug 05 2024 at 15:21):afonso360 requested wasmtime-compiler-reviewers for a review on PR #9079.
Wasmtime GitHub notifications bot (Aug 05 2024 at 15:21):afonso360 requested fitzgen for a review on PR #9079.
Wasmtime GitHub notifications bot (Aug 05 2024 at 15:32):afonso360 edited PR #9079:
:wave: Hey,
The RISC-V ISA has a lot of extensions to support a lot of little things. One example of this, is that it does not support F32 types with the base ISA. To support that we need the F ISA extension.
The RISC-V backend mostly ignored these requirements since both F and D are part of the minimum ISA profile that we request (IMAFD). With this PR we now try to check for those flags when lowering F32 / F64 instructions. (This is fixed in the first commit)
Additionally on the vector side, we only ever checked the vector size, but not the supported types. This means that currently we can lower a F16x8 vector, but we never check that that type is supported by the target CPU. (This is fixed in the second commit)
This is a preparation commit for FP16 support, where we mostly just have to check for a ISA flag to support it. With this change we can now do that in a single place.
Wasmtime GitHub notifications bot (Aug 05 2024 at 17:44):github-actions[bot] commented on PR #9079:
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Wasmtime GitHub notifications bot (Aug 05 2024 at 18:13):cfallin submitted PR review:
LGTM, thanks!
Wasmtime GitHub notifications bot (Aug 05 2024 at 18:28):cfallin merged PR #9079.
Last updated: Dec 23 2024 at 13:07 UTC