afonso360 opened PR #8765 from afonso360:riscv-load-sink
to bytecodealliance:main
:
:wave: Hey,
This PR adds support for merging
{s,u}extend
instructions into a precedingload
.RISC-V doesn't have sinkable loads per se, but the regular load instructions sign / zero extend the loaded values by default. So here we model that by pretending that that is a sinkable load on an extend instruction.
This PR is also a part of #6056. I'm working on that, the first step is to support generating the same code with
load+extend
on all backends as we currently do with the specialized{u,s}loadNN
instructions.
afonso360 requested fitzgen for a review on PR #8765.
afonso360 requested wasmtime-compiler-reviewers for a review on PR #8765.
fitzgen submitted PR review:
Very nice!
fitzgen submitted PR review:
Very nice!
fitzgen created PR review comment:
Maybe add a comment here about the
extend(load())
use case and the asterisk around "sinkable" that you added in the PR description? That seems like good context to have when reading this code.
github-actions[bot] commented on PR #8765:
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afonso360 updated PR #8765.
afonso360 has enabled auto merge for PR #8765.
afonso360 merged PR #8765.
Last updated: Nov 22 2024 at 17:03 UTC