Wasmtime GitHub notifications bot (May 27 2024 at 11:09): Wasmtime GitHub notifications bot (May 27 2024 at 11:09):afonso360 opened PR #8695 from afonso360:riscv-zicond to bytecodealliance:main:
:wave: Hey,
This PR adds support for the ZiCond: Integer Conditional Operations (Chapter 12 of the Unprivileged RISC-V ISA Manual).
This extension adds two instructions that either zero a register, or move one of the arguments, depending on a condition register.
czero.eqz rd, rs1, rs2- Moves zero to a register rd, if the condition rs2 is equal to zero, otherwise moves rs1 to rd.czero.nez rd, rs1, rs2- Moves zero to a register rd, if the condition rs2 is nonzero, otherwise moves rs1 to rdIt doesn't include a full conditional move of two registers, but that is implemented by combining both of the instructions above.
The ISA manual also suggests some interesting instruction sequences for conditional add/sub/and/or/etc... that only contain two instructions.
This PR only implements the base cases. The direct lowerings of the instructions, as well as the full conditional move of two registers. I'm planning on implementing the other sequences at a later date.
Wasmtime GitHub notifications bot (May 27 2024 at 11:09):afonso360 requested wasmtime-default-reviewers for a review on PR #8695.
Wasmtime GitHub notifications bot (May 27 2024 at 11:09):afonso360 requested wasmtime-compiler-reviewers for a review on PR #8695.
Wasmtime GitHub notifications bot (May 27 2024 at 11:09):afonso360 requested fitzgen for a review on PR #8695.
Last updated: Oct 23 2024 at 20:03 UTC