Stream: git-wasmtime

Topic: wasmtime / PR #8253 Cranelift x64 SIMD: some special-case...


view this post on Zulip Wasmtime GitHub notifications bot (Mar 28 2024 at 05:21):

cfallin opened PR #8253 from cfallin:faster-i64x2-vector-construction to bytecodealliance:main:

Sometimes, when in the course of silly optimizations to make the most of one's registers, one might want to pack two i64s into one v128, and one might want to do it without any loads or stores.

In clang targeting Wasm at least, building an i64x2 (with wasm_i64x2_make(a, b) from <wasm_simd128.h>) will generate (i) an i64x2.splat to create a new v128 with lane 0's value in both lanes, then i64x2.replace_lane to put lane 1's value in place. Or, in the case that one of the lanes is zero, it will generate a v128.const 0 then insert the other lane.

Cranelift's lowerings for both of these patterns on x64 are slightly less optimal than they could be.

<!--
Please make sure you include the following information:

Our development process is documented in the Wasmtime book:
https://docs.wasmtime.dev/contributing-development-process.html

Please ensure all communication follows the code of conduct:
https://github.com/bytecodealliance/wasmtime/blob/main/CODE_OF_CONDUCT.md
-->

view this post on Zulip Wasmtime GitHub notifications bot (Mar 28 2024 at 05:21):

cfallin requested wasmtime-compiler-reviewers for a review on PR #8253.

view this post on Zulip Wasmtime GitHub notifications bot (Mar 28 2024 at 05:21):

cfallin requested abrown for a review on PR #8253.

view this post on Zulip Wasmtime GitHub notifications bot (Mar 28 2024 at 08:13):

fitzgen submitted PR review:

LGTM!

view this post on Zulip Wasmtime GitHub notifications bot (Mar 28 2024 at 08:43):

fitzgen merged PR #8253.


Last updated: Nov 22 2024 at 16:03 UTC