Wasmtime GitHub notifications bot (Nov 03 2023 at 13:19): Wasmtime GitHub notifications bot (Nov 03 2023 at 13:19):afonso360 requested cfallin for a review on PR #7471.
Wasmtime GitHub notifications bot (Nov 03 2023 at 13:19):afonso360 requested wasmtime-compiler-reviewers for a review on PR #7471.
Wasmtime GitHub notifications bot (Nov 03 2023 at 13:19):afonso360 opened PR #7471 from afonso360:riscv64-compress-adjust-sp to bytecodealliance:main:
:wave: Hey,
This is a small RISC-V specific follow up to #7470. I noticed that we don't always compress the adjust sp instruction when we could do so.
In the cases where we have build a constant in a temporary register and then
addit to thesp, we encode the registers in a way that was preventing the compressed instruction from being emitted. Currently we only compress anaddif the destination register is the same as the first source register. This is the canonical expansion ofc.add.This PR does two things.
- I've switched the add instruction to have the stack pointer as the first register. i.e.
add sp, t?, sp->add sp, sp, t?. This allows us to compress that instruction with the current emit code.- I've updated the emit code to recognize this pattern and flip the source register when emitting the compressed add. This in theory should allow us to emit this instruction more frequently.
Theoretically we only need the second step to solve this, but I've decided to also change
adjust_spsince its the canonical representation, and at least to me is visually neater having sp as the first source register.This is built on top of #7470, but only the last two commits belong to this PR.
Wasmtime GitHub notifications bot (Nov 03 2023 at 14:47):alexcrichton submitted PR review.
Wasmtime GitHub notifications bot (Nov 03 2023 at 21:18):afonso360 updated PR #7471.
Wasmtime GitHub notifications bot (Nov 03 2023 at 21:19):afonso360 has enabled auto merge for PR #7471.
Wasmtime GitHub notifications bot (Nov 03 2023 at 22:45):afonso360 merged PR #7471.
Last updated: Nov 22 2024 at 17:03 UTC