Stream: git-wasmtime

Topic: wasmtime / PR #7471 riscv64: Find more oportunities to en...


view this post on Zulip Wasmtime GitHub notifications bot (Nov 03 2023 at 13:19):

afonso360 requested cfallin for a review on PR #7471.

view this post on Zulip Wasmtime GitHub notifications bot (Nov 03 2023 at 13:19):

afonso360 requested wasmtime-compiler-reviewers for a review on PR #7471.

view this post on Zulip Wasmtime GitHub notifications bot (Nov 03 2023 at 13:19):

afonso360 opened PR #7471 from afonso360:riscv64-compress-adjust-sp to bytecodealliance:main:

:wave: Hey,

This is a small RISC-V specific follow up to #7470. I noticed that we don't always compress the adjust sp instruction when we could do so.

In the cases where we have build a constant in a temporary register and then add it to the sp, we encode the registers in a way that was preventing the compressed instruction from being emitted. Currently we only compress an add if the destination register is the same as the first source register. This is the canonical expansion of c.add.

This PR does two things.

Theoretically we only need the second step to solve this, but I've decided to also change adjust_sp since its the canonical representation, and at least to me is visually neater having sp as the first source register.

This is built on top of #7470, but only the last two commits belong to this PR.

view this post on Zulip Wasmtime GitHub notifications bot (Nov 03 2023 at 14:47):

alexcrichton submitted PR review.

view this post on Zulip Wasmtime GitHub notifications bot (Nov 03 2023 at 21:18):

afonso360 updated PR #7471.

view this post on Zulip Wasmtime GitHub notifications bot (Nov 03 2023 at 21:19):

afonso360 has enabled auto merge for PR #7471.

view this post on Zulip Wasmtime GitHub notifications bot (Nov 03 2023 at 22:45):

afonso360 merged PR #7471.


Last updated: Dec 23 2024 at 12:05 UTC