Stream: git-wasmtime

Topic: wasmtime / PR #7162 WIP: riscv64: Use the zero register d...

Wasmtime GitHub notifications bot (Oct 05 2023 at 19:39):

alexcrichton opened PR #7162 from alexcrichton:rv64-use-zero-reg to bytecodealliance:main:

This commit is an attempt to use the zero register more often in the riscv64 backend. Currently materializing an iconst 0 value moves the zero register into a general purpose register, and then the general purpose register is used. This means that an extra register is used when it doesn't need to be, for example.

Naively fixing this by returning (zero_reg) during constant emission does not work. One reason this doesn't work is that it introduces vcode aliases to the physical register 0, and during OperandCollector collection the physical register makes its way into normal constraints rather than being a fixed nonallocatable constraint. This is fixable by moving the "resolve alias" phase earlier, for example at the beginning of reg_use rather than lower down in add_operand.

Even after applying such a fix, however, that solution still does not work. This produces situations such as when a 0 constant is returned from a function that the zero register is attempted to be placed into the first return register. These two physical register constraints naturally conflict and nothing is around to generate a move instruction. This happens within OperandCollector meaning it's not easy to generate more instructions at that time.

The "fix", which is incomplete, that this PR implements is to introduce a pseudo-instruction which has a fixed register definition of the physical register zero. This instruction emits no code and is intended to provide a location for regalloc2 to split bundles by automatically inserting a move in the above situation. To get this working however it required removing an assertion in the OperandCollector and ends up violating an invariant of regalloc2 where a virtual register is assigned to a non-allocatable register. This ends up generating instructions which move general purpose registers into the zero register on riscv64, which is unlikely to be what regalloc intended.

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Wasmtime GitHub notifications bot (Oct 10 2023 at 10:33):

alexcrichton closed without merge PR #7162.

Last updated: Oct 23 2024 at 20:03 UTC