alexcrichton opened PR #7145 from alexcrichton:rv64-refactor-select-instrs to bytecodealliance:main:
This commit removes the
IntSelectandSelectRegpseudo-instructions
from the riscv64 backend and consolidates them into theSelect
instruction. Additionally theSelectinstruction is updated to subsume
the functionality of these two previous instructions. NamelySelect
now operates withValueRegsto handle i128 and additionally takes an
IntegerCompareas the condition for the conditional branch to use.This commit touches a fair bit of the backend since conditional
selection of registers was used in quite a few places. The previous
gen_select_*functions are replaced with new typed equivalents of
gen_select_{xreg,vreg,freg,regs}. Furthermore newcmp_*helpers were
added to createIntegerCompareinstructions which sort-of match
conditional branch instructions, or at least the pnemonics they use.Finally since this affected the
selectCLIF instruction itself I went
ahead and did some refactoring there too. Theselectinstruction
creates anIntegerComparefrom its argument to use to generate the
appropriate register selection instruction. This is basically the same
thing thatbrifdoes and now both go through a new helper,
lower_int_compare, which takes aValueand produces an
IntegerComparerepresenting if that value is either true or false.
This enables folding anicmpor anfcmp, for example, directly into
a branching instruction.
alexcrichton requested afonso360 for a review on PR #7145.
alexcrichton requested abrown for a review on PR #7145.
alexcrichton requested wasmtime-compiler-reviewers for a review on PR #7145.
alexcrichton updated PR #7145.
afonso360 submitted PR review:
This looks great to me! Thanks! A small suggestion below.
I also noticed that we are missing support for the
{u,s}{min,max}instructions that I thought were implemented, but apparently not. I'll submit a follow up PR to this one adding them.
afonso360 submitted PR review:
This looks great to me! Thanks! A small suggestion below.
I also noticed that we are missing support for the
{u,s}{min,max}instructions that I thought were implemented, but apparently not. I'll submit a follow up PR to this one adding them.
afonso360 created PR review comment:
Another small optimization here is that we could sign extend
IntCC::EqualandIntCC::NotEqualfor 32bit values. To take advantage of the same sign extend instruction as above.
alexcrichton updated PR #7145.
alexcrichton submitted PR review.
alexcrichton created PR review comment:
Excellent point!
I swear I'm eventually getting back towards icmp (slowly!), and I thought this was a neat optimization in your original PR for icmp. I've added it here as well
alexcrichton has enabled auto merge for PR #7145.
afonso360 submitted PR review.
afonso360 created PR review comment:
Even without
icmpthese refactors are very much appreciated!
alexcrichton updated PR #7145.
alexcrichton has enabled auto merge for PR #7145.
alexcrichton merged PR #7145.
Last updated: Dec 13 2025 at 19:03 UTC