Stream: git-wasmtime

Topic: wasmtime / PR #7080 riscv64: Add the remainder of Zca and...

Wasmtime GitHub notifications bot (Sep 24 2023 at 16:10):

afonso360 opened PR #7080 from afonso360:riscv-c-inst-part-3 to bytecodealliance:main:

:wave: Hey,

This PR completes the Zca and Zcd compressed instruction extensions.

Here's an overview of the new instructions:

• c.srli / c.srai / c.andi / c.li / c.lui these are all fairly regular instruction using the existing CI format or the new CB format. CB also encodes a 6bit signed immediate.
• c.*sp these instructions encode loads or stores from the stack pointer. The immediate is a zero extended 6 bit field so they only encode positive offsets.
• c.fsd / c.fld / c.ld / c.sd / c.lw / c.sw these are the regular compressed loads, the immediate is also zero extended but only 5 bits. And they only support compressible registers.

This PR also includes all of the Zcd instructions. Which are essentially the floating point loads and stores, they are not part of Zca, but are on a separate extension.

We now have complete support for the base C extension (except compressed branches, see https://github.com/bytecodealliance/wasmtime/pull/7047#issuecomment-1723618095). We are still missing Zcb, which I'm planning on adding fairly soon.

Wasmtime GitHub notifications bot (Sep 24 2023 at 16:10):

afonso360 requested abrown for a review on PR #7080.

Wasmtime GitHub notifications bot (Sep 24 2023 at 16:10):

afonso360 requested wasmtime-compiler-reviewers for a review on PR #7080.

Wasmtime GitHub notifications bot (Sep 24 2023 at 16:11):

afonso360 edited PR #7080:

:wave: Hey,

This PR completes the Zca and Zcd compressed instruction extensions.

Here's an overview of the new instructions:

• c.srli / c.srai / c.andi / c.li / c.lui these are all fairly regular instruction using the existing CI format or the new CB format. CB encodes a 6bit signed immediate and one compressed register.
• c.*sp these instructions encode loads or stores from the stack pointer. The immediate is a zero extended 6 bit field so they only encode positive offsets.
• c.fsd / c.fld / c.ld / c.sd / c.lw / c.sw these are the regular compressed loads, the immediate is also zero extended but only 5 bits. And they only support compressible registers.

This PR also includes all of the Zcd instructions. Which are essentially the floating point loads and stores, they are not part of Zca, but are on a separate extension.

We now have complete support for the base C extension (except compressed branches, see https://github.com/bytecodealliance/wasmtime/pull/7047#issuecomment-1723618095). We are still missing Zcb, which I'm planning on adding fairly soon.

Wasmtime GitHub notifications bot (Sep 25 2023 at 14:35):

alexcrichton submitted PR review:

:+1:

Wasmtime GitHub notifications bot (Sep 25 2023 at 15:27):

alexcrichton merged PR #7080.

Last updated: Dec 23 2024 at 12:05 UTC