Wasmtime GitHub notifications bot (Sep 02 2023 at 14:14): Wasmtime GitHub notifications bot (Sep 02 2023 at 14:14):afonso360 opened PR #6956 from afonso360:riscv-reorder-regs to bytecodealliance:main:
:wave: Hey,
This is a preparation commit for the introduction of compressed instructions in the RISC-V backend.
Some compressed instruction formats can only represent a limited range of addressable registers (x8 to x15). Outside of those ranges we have to fallback to the non compressed version of the instruction.
Thus, this commit reorders the register allocation preference to try an use those registers as much as possible. In order to maximize the opportunities to emit compressed instructions.
The preference list is now roughly as follows:
- Compressible Caller Saved registers.
- Non-Compressible Caller Saved registers.
- Compressible Callee Saved registers.
- Non-Compressible Callee Saved registers.
This applies for both Integer and Floating point registers. Vector registers currently are all caller saved, so it doesn't make much of a difference.
Wasmtime GitHub notifications bot (Sep 02 2023 at 14:14):afonso360 requested wasmtime-compiler-reviewers for a review on PR #6956.
Wasmtime GitHub notifications bot (Sep 02 2023 at 14:14):afonso360 requested cfallin for a review on PR #6956.
Wasmtime GitHub notifications bot (Sep 02 2023 at 14:14):afonso360 edited PR #6956:
:wave: Hey,
This is a preparation commit for the introduction of compressed instructions in the RISC-V backend.
Some compressed instruction formats can only represent a limited range of registers (x8 to x15). Outside of those ranges we have to fallback to the non compressed version of the instruction.
Thus, this commit reorders the register allocation preference to try an use those registers as much as possible. In order to maximize the opportunities to emit compressed instructions.
The preference list is now roughly as follows:
- Compressible Caller Saved registers.
- Non-Compressible Caller Saved registers.
- Compressible Callee Saved registers.
- Non-Compressible Callee Saved registers.
This applies for both Integer and Floating point registers. Vector registers currently are all caller saved, so it doesn't make much of a difference.
Wasmtime GitHub notifications bot (Sep 02 2023 at 14:26):afonso360 edited PR #6956:
:wave: Hey,
This is a preparation commit for the introduction of compressed instructions in the RISC-V backend.
Some compressed instruction formats can only represent a limited range of registers (x8 to x15). Outside of those ranges we have to fallback to the non compressed version of the instruction.
Thus, this commit reorders the register allocation preference to try an use those registers as much as possible. In order to maximize the opportunities to emit compressed instructions.
The preference list is now roughly as follows:
- Compressible Caller Saved registers.
- Non-Compressible Caller Saved registers.
- Compressible Callee Saved registers.
- Non-Compressible Callee Saved registers.
Only Compressible Caller Saved registers are marked as preferred registers in regalloc, the rest are listed in preferred order (not entirely sure if that helps or not).
This applies for both Integer and Floating point registers. Vector registers currently are all caller saved, so it doesn't make much of a difference.
Wasmtime GitHub notifications bot (Sep 02 2023 at 14:26):afonso360 edited PR #6956:
:wave: Hey,
This is a preparation commit for the introduction of compressed instructions in the RISC-V backend.
Some compressed instruction formats can only represent a limited range of registers (x8 to x15). Outside of those ranges we have to fallback to the non compressed version of the instruction.
Thus, this commit reorders the register allocation preference to try an use those registers as much as possible. In order to maximize the opportunities to emit compressed instructions.
The preference list is now roughly as follows:
- Compressible Caller Saved registers.
- Non-Compressible Caller Saved registers.
- Compressible Callee Saved registers.
- Non-Compressible Callee Saved registers.
Only Compressible Caller Saved registers (1) are marked as preferred registers in regalloc, the rest are listed in preferred order (not entirely sure if that helps or not).
This applies for both Integer and Floating point registers. Vector registers currently are all caller saved, so it doesn't make much of a difference.
Wasmtime GitHub notifications bot (Sep 02 2023 at 14:27):afonso360 edited PR #6956:
:wave: Hey,
This is a preparation commit for the introduction of compressed instructions in the RISC-V backend.
Some compressed instruction formats can only represent a limited range of registers (x8 to x15). Outside of those ranges we have to fallback to the non compressed version of the instruction.
Thus, this commit reorders the register allocation preference to try an use those registers as much as possible. In order to maximize the opportunities to emit compressed instructions.
The preference list is now roughly as follows:
- Compressible Caller Saved registers.
- Non-Compressible Caller Saved registers.
- Compressible Callee Saved registers.
- Non-Compressible Callee Saved registers.
Only Compressible Caller Saved registers (1) are marked as preferred registers in regalloc, the rest are listed in order but marked as non preferred (not entirely sure if that helps or not).
This applies for both Integer and Floating point registers. Vector registers currently are all caller saved, so it doesn't make much of a difference.
Wasmtime GitHub notifications bot (Sep 02 2023 at 14:27):afonso360 edited PR #6956:
:wave: Hey,
This is a preparation commit for the introduction of compressed instructions in the RISC-V backend.
Some compressed instruction formats can only represent a limited range of registers (x8 to x15). Outside of those ranges we have to fallback to the non compressed version of the instruction.
Thus, this commit reorders the register allocation preference to try an use those registers as much as possible. In order to maximize the opportunities to emit compressed instructions.
The preference list is now roughly as follows:
- Compressible Caller Saved registers.
- Non-Compressible Caller Saved registers.
- Compressible Callee Saved registers.
- Non-Compressible Callee Saved registers.
Only Compressible Caller Saved registers (1) are marked as preferred registers in regalloc, the rest are marked as non preferred but listed in order (2, 3, 4) (not entirely sure if that helps or not).
This applies for both Integer and Floating point registers. Vector registers currently are all caller saved, so it doesn't make much of a difference.
Wasmtime GitHub notifications bot (Sep 06 2023 at 15:41):alexcrichton submitted PR review:
Looks reasonable to me, thanks!
Wasmtime GitHub notifications bot (Sep 06 2023 at 21:34):afonso360 updated PR #6956.
Wasmtime GitHub notifications bot (Sep 06 2023 at 21:34):afonso360 has enabled auto merge for PR #6956.
Wasmtime GitHub notifications bot (Sep 06 2023 at 22:56):afonso360 merged PR #6956.
Last updated: Oct 23 2024 at 20:03 UTC