Wasmtime GitHub notifications bot (Aug 29 2023 at 16:49): Wasmtime GitHub notifications bot (Aug 29 2023 at 16:49):afonso360 requested wasmtime-default-reviewers for a review on PR #6924.
Wasmtime GitHub notifications bot (Aug 29 2023 at 16:49):afonso360 requested elliottt for a review on PR #6924.
Wasmtime GitHub notifications bot (Aug 29 2023 at 16:56):afonso360 requested wasmtime-compiler-reviewers for a review on PR #6924.
Wasmtime GitHub notifications bot (Aug 29 2023 at 16:56):afonso360 edited PR #6924:
:wave: Hey,
This PR implements the floating point conversion instructions (
fvdemote,fvpromote_low,fcvt_{to,from}_{u,s}int{,_sat}) on the RISC-V backend.All of the underlying instructions were implemented in #6920, so we don't need to introduce new ones.
:tada: With this PR we now have SIMD fully implemented for RISC-V:tada:
There is 1 test that is not passing yet, but I think that is due to a NaN payload bit mismatch that is allowed by the spec. But I'm going to open a separate issue to confirm that.
(This PR is built on top of #6920 so we need to merge that one first)
Wasmtime GitHub notifications bot (Aug 29 2023 at 16:56):afonso360 opened PR #6924 from afonso360:riscv-simd-ftoi to bytecodealliance:main:
:wave: Hey,
This PR implements the floating point conversion instructions (
fvdemote,fvpromote_low,fcvt_{to,from}_{u,s}int{,_sat}) on the RISC-V backend.All of the underlying instructions were implemented in #6920, so we don't need to introduce new ones.
:tada: With this PR we now have SIMD fully implemented for RISC-V:tada:
There is 1 test that is not passing yet, but I think that is due to a NaN payload bit mismatch that is allowed by the spec. But I'm going to open a separate issue to confirm that.
(This PR is built on top of #6920 so we need to merge that one first)
Wasmtime GitHub notifications bot (Aug 29 2023 at 16:59):afonso360 edited PR #6924:
:wave: Hey,
This PR implements the floating point conversion instructions (
fvdemote,fvpromote_low,fcvt_{to,from}_{u,s}int{,_sat}) on the RISC-V backend.All of the underlying instructions were implemented in #6920, so we don't need to introduce new ones.
Almost all instructions match 1-to-1 with the WASM spec, except
fcvt_to_{u,s}int_sat, where NaN's need to be manually zeroed out. And onfvdemoteRISC-V leaves the upper lanes undefined, so we also zero them out manually.
:tada: With this PR we now have SIMD fully implemented for RISC-V:tada:
There is 1 test that is not passing yet, but I think that is due to a NaN payload bit mismatch that is allowed by the spec. But I'm going to open a separate issue to confirm that.
(This PR is built on top of #6920 so we need to merge that one first)
Wasmtime GitHub notifications bot (Aug 30 2023 at 20:27):afonso360 updated PR #6924.
Wasmtime GitHub notifications bot (Aug 30 2023 at 20:29):afonso360 edited PR #6924:
:wave: Hey,
This PR implements the floating point conversion instructions (
fvdemote,fvpromote_low,fcvt_{to,from}_{u,s}int{,_sat}) on the RISC-V backend.Almost all instructions match 1-to-1 with the WASM spec, except
fcvt_to_{u,s}int_sat, where NaN's need to be manually zeroed out. And onfvdemoteRISC-V leaves the upper lanes undefined, so we also zero them out manually.
:tada: With this PR we now have SIMD fully implemented for RISC-V:tada:
There is 1 test that is not passing yet, but I think that is due to a NaN payload bit mismatch that is allowed by the spec. But I'm going to open a separate issue to confirm that.
(This PR is built on top of #6920 so we need to merge that one first)
Wasmtime GitHub notifications bot (Aug 30 2023 at 20:37):alexcrichton submitted PR review:
:confetti: nice!
You've done quite a lot of work on this backend and it's very much appreciated, thank you!
Wasmtime GitHub notifications bot (Aug 30 2023 at 20:42):alexcrichton has enabled auto merge for PR #6924.
Wasmtime GitHub notifications bot (Aug 30 2023 at 21:54):alexcrichton merged PR #6924.
Last updated: Oct 23 2024 at 20:03 UTC