Stream: git-wasmtime

Topic: wasmtime / PR #6815 riscv64: Add SIMD IFMA instruction su...

view this post on Zulip Wasmtime GitHub notifications bot (Aug 07 2023 at 17:40):

afonso360 opened PR #6815 from afonso360:riscv-ifma to bytecodealliance:main:

:wave: Hey,

This PR adds support for SIMD integer fused multiply add/subtract instructions to RISC-V. These instructions modify one of the source registers, so I've added a new instruction format for it.

We have 4 variants of this instruction (§11.13. Vector Single-Width Integer Multiply-Add Instructions), I've only used two, since it looks like vmadd/vnmsub match the same pattern but just modify different registers. I'm not entirely sure how to expose this, since it looks like just a regalloc optimization.

Additionally I couldn't find a way to match isub+imul, It looks like vnmsac does not match that, but maybe I'm missing something!

view this post on Zulip Wasmtime GitHub notifications bot (Aug 07 2023 at 17:40):

afonso360 requested jameysharp for a review on PR #6815.

view this post on Zulip Wasmtime GitHub notifications bot (Aug 07 2023 at 17:40):

afonso360 requested wasmtime-compiler-reviewers for a review on PR #6815.

view this post on Zulip Wasmtime GitHub notifications bot (Aug 09 2023 at 16:48):

jameysharp submitted PR review:

Looks good!

These patterns are already being generated by fuzzgen, right? I've lost track of what works right now.

While reading this it occurred to me that someday we ought to have a lot more egraph rules for splat, such as rewriting (imul (splat x) (splat y)) to (splat (imul x y)). Those should probably go in cranelift/codegen/src/opts/vector.isle, and move some existing rules from extends.isle` there too I think.

view this post on Zulip Wasmtime GitHub notifications bot (Aug 09 2023 at 22:50):

afonso360 merged PR #6815.

Last updated: Oct 23 2024 at 20:03 UTC