fitzgen opened PR #6780 from fitzgen:fix-riscv64-gen-add-imm
to bytecodealliance:main
:
It was generating bit-wise and instructions instead of addition instructions.
While we are at it, use field literal short hand for a struct literal in riscv64 instruction emission.
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fitzgen requested jameysharp for a review on PR #6780.
fitzgen requested wasmtime-compiler-reviewers for a review on PR #6780.
fitzgen requested alexcrichton for a review on PR #6780.
fitzgen updated PR #6780.
alexcrichton submitted PR review.
fitzgen merged PR #6780.
Last updated: Dec 23 2024 at 12:05 UTC