afonso360 opened PR #6598 from afonso360:riscv-simd-misc-1
to bytecodealliance:main
:
:wave: Hey,
This is a number of changes that are all quite small and unrelated to each other but allow us to enable a few more SIMD tests. Each commit is unrelated to other commits, so reviewing them individually might make more sense.
The vector select instruction is implemented the preexisting scalar version of the instruction that uses a conditional branch over a move instruction. Vector move instructions were implemented in #6568 so we just needed to allocate a vector register and the existing code already works!
None of these commits have any relation to the
memory64
tests, I just tested enabling those and it looks like we already implement all required instructions.
afonso360 requested elliottt for a review on PR #6598.
afonso360 requested wasmtime-compiler-reviewers for a review on PR #6598.
afonso360 requested wasmtime-default-reviewers for a review on PR #6598.
afonso360 updated PR #6598.
afonso360 updated PR #6598.
afonso360 updated PR #6598.
alexcrichton submitted PR review:
Nice!
alexcrichton submitted PR review:
Nice!
alexcrichton created PR review comment:
This may be a bit of a dated copy/paste now that SSSE3 is the baseline for x86_64 simd support, but I've only been doing this in tests that exercise post-SSE2 instructions which I'm not sure if
select
does, but basically it's ok to delete this line if you'd like
afonso360 updated PR #6598.
afonso360 has enabled auto merge for PR #6598.
afonso360 updated PR #6598.
afonso360 merged PR #6598.
Last updated: Dec 23 2024 at 13:07 UTC