Stream: git-wasmtime

Topic: wasmtime / PR #6568 riscv64: Implement `iadd_pairwise`

Wasmtime GitHub notifications bot (Jun 12 2023 at 23:47):

afonso360 opened PR #6568 from afonso360:riscv-simd-iadd-pairwise to bytecodealliance:main:

:wave: Hey,

This PR implements both the move instruction for vector registers and iadd_pairwise.

We can't really implement iadd_pairwise in the best way possible, since that requires supporting LMUL > 1 which dynamically changes how many registers are available. (At least as far as I know, If regalloc supports this it would be nice to start using it)

Wasmtime GitHub notifications bot (Jun 12 2023 at 23:47):

afonso360 requested fitzgen for a review on PR #6568.

Wasmtime GitHub notifications bot (Jun 12 2023 at 23:47):

afonso360 requested wasmtime-compiler-reviewers for a review on PR #6568.

Wasmtime GitHub notifications bot (Jun 12 2023 at 23:47):

afonso360 requested wasmtime-default-reviewers for a review on PR #6568.

Wasmtime GitHub notifications bot (Jun 12 2023 at 23:48):

afonso360 created PR review comment:

The vslideup instruction both modifies the destination register and also has the requirement that none of the input registers must be the same as the destination register.

I've used reg_late_use and reg_reuse_def to model this, but this seems wrong, and it also always emits a move before the instruction even when the register is otherwise unused, so there's probably a better way of expressing this which I'm not entirely sure how

Wasmtime GitHub notifications bot (Jun 12 2023 at 23:52):

afonso360 edited PR review comment.

Wasmtime GitHub notifications bot (Jun 12 2023 at 23:54):

afonso360 edited PR review comment.

Wasmtime GitHub notifications bot (Jun 13 2023 at 02:24):

cfallin submitted PR review.

Wasmtime GitHub notifications bot (Jun 13 2023 at 02:24):

cfallin submitted PR review.

Wasmtime GitHub notifications bot (Jun 13 2023 at 02:24):

cfallin created PR review comment:

I'm not sure I understand the intended semantics here: src and dst (vd_src and vd, rather) must not overlap, but vd is also a reuse of vd_src? Or is the non-overlap constraint between vs2 and vd?

Wasmtime GitHub notifications bot (Jun 13 2023 at 08:53):

afonso360 created PR review comment:

Oops, I could have written that better. vd must be the same as vd_src (since they are encoded in the same field), and none of the other inputs (vs2 and vm) must be the same register as vd.

vm (The mask register) is slightly hidden here since it's not always applicable, but when it is, it's a fixed_use(v0)

Wasmtime GitHub notifications bot (Jun 13 2023 at 15:21):

cfallin created PR review comment:

Ah, OK. The right way to encode that is probably to use a late-use on vs2 (and on vm when present), rather than on vd_src, I think.

Wasmtime GitHub notifications bot (Jun 13 2023 at 18:38):

afonso360 updated PR #6568.

Wasmtime GitHub notifications bot (Jun 13 2023 at 18:41):

afonso360 created PR review comment:

:+1: I'm not entirely sure I did the right thing. I also couldn't find something along the lines of reg_fixed_late_use for vm, does regalloc support encoding multiple constraints by calling reg_fixed_use and reg_late_use on the same VReg?

Wasmtime GitHub notifications bot (Jun 13 2023 at 18:45):

cfallin created PR review comment:

Yep, it should be possible to do that -- if it's not on the OperandCollector API we can add it. The early/late ("position"), use/def ("kind"), and fixed/any/reg/stack ("constraint") are all orthogonal fields of the Operand.

Wasmtime GitHub notifications bot (Jun 13 2023 at 19:02):

afonso360 updated PR #6568.

Wasmtime GitHub notifications bot (Jun 14 2023 at 11:40):

afonso360 updated PR #6568.

Wasmtime GitHub notifications bot (Jun 16 2023 at 15:18):

afonso360 requested cfallin for a review on PR #6568.

Wasmtime GitHub notifications bot (Jun 16 2023 at 15:55):

cfallin submitted PR review.

Wasmtime GitHub notifications bot (Jun 16 2023 at 16:36):

cfallin merged PR #6568.

Last updated: Oct 23 2024 at 20:03 UTC