afonso360 opened PR #6515 from afonso360:riscv-simd-swizzle-shuffle
to bytecodealliance:main
:
:wave: Hey,
This PR implements the
swizzle
andshuffle
instructions in the RISC-V backend.
swizzle
maps directly intovrgather
with a SEW of 8, so that's a fairly simple implementation. Forshuffle
we have to do twovrgathers
one for values in the range of the first register and the second for values in range of the second register and merge them together.I double checked the
shuffle
implementation, and it seems to match what v8 does.I also didn't try to include optimized lowerings of
swizzle
orshuffle
.
vrgather
is a somewhat special instruction in that it forbids the destination register from being the same as any of the source registers (including the mask register). I've modeled this as anearly_def
, which seems to be correct based on what I've read from regalloc2 docs, but I'm not 100% sure.There are a few other instructions like this, but none that we have implemented yet.
afonso360 requested fitzgen for a review on PR #6515.
afonso360 requested wasmtime-compiler-reviewers for a review on PR #6515.
afonso360 requested wasmtime-default-reviewers for a review on PR #6515.
afonso360 edited PR #6515:
:wave: Hey,
This PR implements the
swizzle
andshuffle
instructions in the RISC-V backend.
swizzle
maps directly ontovrgather
with a SEW of 8, so that's a fairly simple implementation. Forshuffle
we have to do twovrgathers
one for values in the range of the first register and the second for values in range of the second register and merge them together.I double checked the
shuffle
implementation, and it seems to match what v8 does.I also didn't try to include optimized lowerings of
swizzle
orshuffle
.
vrgather
is a somewhat special instruction in that it forbids the destination register from being the same as any of the source registers (including the mask register). I've modeled this as anearly_def
, which seems to be correct based on what I've read from regalloc2 docs, but I'm not 100% sure.There are a few other instructions like this, but none that we have implemented yet.
afonso360 edited PR #6515:
:wave: Hey,
This PR implements the
swizzle
andshuffle
instructions in the RISC-V backend.
swizzle
maps directly ontovrgather
with a SEW of 8, so that's a fairly simple implementation. Forshuffle
we have to do twovrgathers
one for values in the range of the first register and the second for values in range of the second register and merge them together.I double checked the
shuffle
implementation, and it seems to match what v8 does.
vrgather
is a somewhat special instruction in that it forbids the destination register from being the same as any of the source registers (including the mask register). I've modeled this as anearly_def
, which seems to be correct based on what I've read from regalloc2 docs, but I'm not 100% sure.There are a few other instructions like this, but none that we have implemented yet.
fitzgen submitted PR review:
LGTM with the following little nitpicks. Thanks!
fitzgen submitted PR review:
LGTM with the following little nitpicks. Thanks!
fitzgen created PR review comment:
Can you either resolve this TODO in this PR or turn it into
TODO(#1234)
with a reference to a follow up issue?
fitzgen created PR review comment:
Nitpick: missing trailing newline
afonso360 updated PR #6515.
afonso360 has enabled auto merge for PR #6515.
afonso360 merged PR #6515.
Last updated: Nov 22 2024 at 16:03 UTC