Stream: git-wasmtime

Topic: wasmtime / PR #6430 riscv64: Implement SIMD saturating ar...

Wasmtime GitHub notifications bot (May 22 2023 at 18:57):

afonso360 opened PR #6430 from afonso360:riscv-sat-arith-minmax to bytecodealliance:main:

:wave: Hey,

This PR Implements the saturating arithmetic ({u,s}{add,sub}_sat) and min/max ({u,s}{min,max}) instructions.

Only the saturating arithmetic functions are tested via WASM tests. The min/max instruction testsuites have other instructions mixed in that will be implemented in a future PR so we can't enable them yet. These are currently only tested via cranelift tests.

I've also added i128 tests for min/max since I accidentally disabled these and found we didn't have anything catching that case.

Wasmtime GitHub notifications bot (May 22 2023 at 18:57):

afonso360 requested jameysharp for a review on PR #6430.

Wasmtime GitHub notifications bot (May 22 2023 at 18:57):

afonso360 requested wasmtime-compiler-reviewers for a review on PR #6430.

Wasmtime GitHub notifications bot (May 22 2023 at 18:57):

afonso360 requested wasmtime-default-reviewers for a review on PR #6430.

Wasmtime GitHub notifications bot (May 22 2023 at 22:27):

alexcrichton submitted PR review.

Wasmtime GitHub notifications bot (May 22 2023 at 22:27):

alexcrichton submitted PR review.

Wasmtime GitHub notifications bot (May 22 2023 at 22:27):

alexcrichton created PR review comment:

Stray thought, but the x64 backend has different types for Gpr and Xmm which represent a type-level distinction for different classes of registers. I've found that it's actually worked quite well for x64 and it's saved me a few times from mistakes. I realized I should be carefully reading the rules that use *_vx instructions to ensure the variable bound by splat comes second instead of first by accident (since I think that would compile past ISLE but wouldn't get past debug asserts perhaps in the backend).

Having this sort of distinction though is a pretty large refactoring so definitely not necessary on this PR, but perhaps something to consider if you also find yourself trying to carefully ensure each register goes to the right spot.

Wasmtime GitHub notifications bot (May 23 2023 at 15:55):

afonso360 created PR review comment:

Yeah, that sounds like a good idea! And I've definitely had that happen to me. Not with .vx, but passing an F register into a .vx opcode.

It should be fairly easy to start at least with the vector rules and helpers. I'm going to give that a try.

Wasmtime GitHub notifications bot (May 23 2023 at 15:56):

afonso360 edited PR review comment.

Wasmtime GitHub notifications bot (May 23 2023 at 16:32):

afonso360 merged PR #6430.

Last updated: Dec 23 2024 at 13:07 UTC