afonso360 opened PR #6367 from afonso360:riscv-vx
to bytecodealliance:main
:
:wave: Hey,
This PR introduces
.vx
format opcodes, thesesplat
an X or F register and perform the respective operation.I've only added
vadd
,vsub
andvrsub
, but these are available for most opcodes.Additionally with the addition of
ineg
we now pass thesimd_*_arith.wast
test suites :tada: . I'm planning on enabling those when both this and the RegClass PR's are merged.
afonso360 requested elliottt for a review on PR #6367.
afonso360 requested wasmtime-compiler-reviewers for a review on PR #6367.
afonso360 created PR review comment:
This assert triggers since we are now trying to format some integer registers and I didn't change the pretty printer. However this function gets removed in #6366, so I figured it's easier to wait for that to be merged and rebase this.
elliottt submitted PR review:
Just one quick question about the funct6 values for Vadd and Vsub, otherwise this looks great!
elliottt submitted PR review:
Just one quick question about the funct6 values for Vadd and Vsub, otherwise this looks great!
elliottt created PR review comment:
What needs to change for these to be converted to
Vector
?
elliottt created PR review comment:
It's surprising that the vector/vector and vector/scalar combinations have the same
funct6
value. Does something else end up distinguishing those cases?
afonso360 created PR review comment:
Nothing really, just waiting on https://github.com/bytecodealliance/wasmtime/pull/6366 to be merged.
afonso360 created PR review comment:
Yes,
funct3
usually dictates the source/destination register types for most opcodes.
afonso360 edited PR review comment.
elliottt submitted PR review:
Looks great, thank you Afonso!
afonso360 updated PR #6367.
afonso360 has enabled auto merge for PR #6367.
afonso360 merged PR #6367.
Last updated: Dec 23 2024 at 12:05 UTC